467 lines
15 KiB
C++
467 lines
15 KiB
C++
/***************************************************************************************************
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* Copyright (c) 2017 - 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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**************************************************************************************************/
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/*! \file
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\brief Architecture-specific operators on memory added for SM80
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*/
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#pragma once
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#include "cutlass/cutlass.h"
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#include "cutlass/complex.h"
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#include "cutlass/arch/memory.h"
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#include "cutlass/arch/memory_sm75.h"
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#include "cutlass/arch/cache_operation.h"
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800)
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#define CUDA_CP_ASYNC_ACTIVATED 1
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#else
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#define CUDA_CP_ASYNC_ACTIVATED 0
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#endif
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namespace cutlass {
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namespace arch {
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////////////////////////////////////////////////////////////////////////////////////////////////////
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/// Initiates an asynchronous copy from global memory to shared memory.
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///
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/// LDGSTS
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///
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template <
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/// Size of the access in bytes
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int SizeInBytes,
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/// Cache operation
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CacheOperation::Kind cache_op = CacheOperation::Always>
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struct cp_async;
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/// Initiates an asynchronous copy from global memory to shared memory. Rather than predicate
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/// the entire transfer, zeros are written to SMEM if the guard predicate is false.
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///
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/// LDGSTS
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///
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template <
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/// Size of the access in bytes
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int SizeInBytes,
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/// Cache operation
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CacheOperation::Kind cache_op = CacheOperation::Always>
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struct cp_async_zfill;
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/// Initiates an asynchronous copy from global memory to shared memory. Rather than predicate
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/// the entire transfer, nans (0x7eff) are written to SMEM if the guard predicate is false.
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///
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/// LDGSTS
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///
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template <
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/// Size of the access in bytes
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int SizeInBytes,
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/// Cache operation
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CacheOperation::Kind cache_op = CacheOperation::Always>
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struct cp_async_nan;
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/// Either 0 or 1 are written to SMEM based on input element type
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/// Used for diagonal elements of triangular matrix of BLAS3 functions
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///
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/// STS
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///
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template <
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/// Type of Element
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typename Element,
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/// If the data is for a Hermitian matrix diagonal
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bool IsHermitianData = false>
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struct cp_async_diag;
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static const uint32_t OOB_NAN_F16 = 0x7eff;
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static const uint32_t OOB_NAN_F16x2 = ((OOB_NAN_F16 << 16) | OOB_NAN_F16);
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////////////////////////////////////////////////////////////////////////////////////////////////////
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/// Partial specialization
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template <
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/// Size of the access in bytes
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int SizeInBytes>
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struct cp_async<SizeInBytes, CacheOperation::Always> {
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/// Copy
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CUTLASS_DEVICE
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cp_async(void *smem_ptr, void const *global_ptr, bool pred_guard = true) {
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#if CUDA_CP_ASYNC_ACTIVATED
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// Make sure the size is supported.
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static_assert((SizeInBytes == 4 || SizeInBytes == 8 || SizeInBytes == 16),
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"Size is not supported");
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unsigned smem_int_ptr = cutlass_get_smem_pointer(smem_ptr);
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asm volatile(
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"{\n"
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" .reg .pred p;\n"
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" setp.ne.b32 p, %0, 0;\n"
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#if CUTLASS_ENABLE_L2_PREFETCH
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" @p cp.async.ca.shared.global.L2::128B [%1], [%2], %3;\n"
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#else
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" @p cp.async.ca.shared.global [%1], [%2], %3;\n"
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#endif
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"}\n" ::"r"((int)pred_guard),
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"r"(smem_int_ptr), "l"(global_ptr), "n"(SizeInBytes));
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#else
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using AccessType = Array<uint8_t, SizeInBytes>;
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if (pred_guard) {
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*static_cast<AccessType *>(smem_ptr) = *static_cast<AccessType const *>(global_ptr);
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}
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#endif
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}
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};
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/// Partial specialization
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template <
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/// Size of the access in bytes
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int SizeInBytes>
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struct cp_async_zfill<SizeInBytes, CacheOperation::Always> {
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/// Copy with zero fill
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CUTLASS_DEVICE
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cp_async_zfill(void *smem_ptr, void const *global_ptr, bool pred_guard) {
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#if CUDA_CP_ASYNC_ACTIVATED
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// Make sure the size is supported.
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static_assert((SizeInBytes == 4 || SizeInBytes == 8 || SizeInBytes == 16),
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"Size is not supported");
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unsigned smem_int_ptr = cutlass_get_smem_pointer(smem_ptr);
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int src_in_bytes = (pred_guard ? SizeInBytes : 0);
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asm volatile(
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#if CUTLASS_ENABLE_L2_PREFETCH
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"cp.async.ca.shared.global.L2::128B [%0], [%1], %2, %3;\n" ::"r"(smem_int_ptr),
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#else
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"cp.async.ca.shared.global [%0], [%1], %2, %3;\n" ::"r"(smem_int_ptr),
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#endif
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"l"(global_ptr), "n"(SizeInBytes), "r"(src_in_bytes));
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#else
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using AccessType = Array<uint8_t, SizeInBytes>;
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if (pred_guard) {
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*static_cast<AccessType *>(smem_ptr) = *static_cast<AccessType const *>(global_ptr);
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}
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else {
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AccessType zeros;
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zeros.clear();
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*static_cast<AccessType *>(smem_ptr) = zeros;
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}
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#endif
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}
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};
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/// Partial specialization
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template <>
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struct cp_async_nan<16, CacheOperation::Always> {
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static int const kSizeInBytes = 16;
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/// Copy with nan fill
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CUTLASS_DEVICE
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cp_async_nan(void *smem_ptr, void const *global_ptr, bool pred_guard) {
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#if CUDA_CP_ASYNC_ACTIVATED
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static __constant__ uint4 OOB_NAN_F16x8 = {OOB_NAN_F16x2, OOB_NAN_F16x2,
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OOB_NAN_F16x2, OOB_NAN_F16x2};
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unsigned smem_int_ptr = cutlass_get_smem_pointer(smem_ptr);
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asm volatile(
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"{\n"
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" .reg .pred p;\n"
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" setp.ne.b32 p, %0, 0;\n"
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#if CUTLASS_ENABLE_L2_PREFETCH
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" @p cp.async.ca.shared.global.L2::128B [%1], [%2], %3;\n"
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#else
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" @p cp.async.ca.shared.global [%1], [%2], %3;\n"
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#endif
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" @!p st.shared.v4.u32 [%1], {%4, %5, %6, %7};\n"
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"}\n"
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:
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: "r"((int)pred_guard), "r"(smem_int_ptr), "l"(global_ptr),
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"n"(kSizeInBytes), "r"(OOB_NAN_F16x8.x), "r"(OOB_NAN_F16x8.y), "r"(OOB_NAN_F16x8.z),
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"r"(OOB_NAN_F16x8.w));
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#else
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CUTLASS_UNUSED(smem_ptr);
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CUTLASS_UNUSED(global_ptr);
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CUTLASS_UNUSED(pred_guard);
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CUTLASS_NOT_IMPLEMENTED();
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#endif
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}
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};
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/// Partial specialization to write one (1)
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template<typename Element_>
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struct cp_async_diag <Element_, false> {
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using Element = Element_;
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CUTLASS_DEVICE
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cp_async_diag(void *smem_ptr) {
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#if CUDA_CP_ASYNC_ACTIVATED
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/// Values for the diagonal elements of the triangular input matrix
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static __constant__ uint2 DIAG_DATA_DOUBLE_ONE = {0x3ff00000, 0x00000000};
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static __constant__ uint1 DIAG_DATA_FLOAT_ONE = {0x3f800000};
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static __constant__ uint1 DIAG_DATA_ZERO = {0x00000000};
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unsigned smem_int_ptr = cutlass_get_smem_pointer(smem_ptr);
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if (platform::is_same<Element, complex<double>>::value) {
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asm volatile("st.shared.v4.u32 [%0], {%1, %2, %3, %4};\n"
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: :
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"r"(smem_int_ptr), "r"(DIAG_DATA_DOUBLE_ONE.y), "r"(DIAG_DATA_DOUBLE_ONE.x),
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"r"(DIAG_DATA_ZERO.x), "r"(DIAG_DATA_ZERO.x));
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} else if (platform::is_same<Element, complex<float>>::value) {
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asm volatile("st.shared.v2.u32 [%0], {%1, %2};\n"
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: :
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"r"(smem_int_ptr), "r"(DIAG_DATA_FLOAT_ONE.x), "r"(DIAG_DATA_ZERO.x));
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} else if (platform::is_same<Element, double>::value) {
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asm volatile("st.shared.v2.u32 [%0], {%1, %2};\n"
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: :
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"r"(smem_int_ptr), "r"(DIAG_DATA_DOUBLE_ONE.y),"r"(DIAG_DATA_DOUBLE_ONE.x));
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} else if (platform::is_same<Element, float>::value) {
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asm volatile("st.shared.u32 [%0], %1;\n"
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: :
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"r"(smem_int_ptr), "r"(DIAG_DATA_FLOAT_ONE.x));
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} else {
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CUTLASS_UNUSED(smem_int_ptr);
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CUTLASS_NOT_IMPLEMENTED();
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}
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#else
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CUTLASS_UNUSED(smem_ptr);
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CUTLASS_NOT_IMPLEMENTED();
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#endif
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}
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};
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/// Partial specialization to write zero for the imaginary part of Hermitian data
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template<typename Element_>
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struct cp_async_diag <Element_, true> {
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using Element = Element_;
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CUTLASS_DEVICE
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cp_async_diag(void *smem_ptr) {
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#if CUDA_CP_ASYNC_ACTIVATED
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/// Values for the diagonal elements of the triangular input matrix
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static __constant__ uint1 DIAG_DATA_ZERO = {0x00000000};
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unsigned smem_int_ptr = cutlass_get_smem_pointer(smem_ptr);
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if (platform::is_same<Element, complex<double>>::value) {
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asm volatile("st.shared.v2.u32 [%0], {%1, %2};\n"
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: :
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"r"(smem_int_ptr), "r"(DIAG_DATA_ZERO.x), "r"(DIAG_DATA_ZERO.x));
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} else if (platform::is_same<Element, complex<float>>::value) {
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asm volatile("st.shared.u32 [%0], %1;\n"
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: :
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"r"(smem_int_ptr), "r"(DIAG_DATA_ZERO.x));
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} else {
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CUTLASS_UNUSED(smem_int_ptr);
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CUTLASS_NOT_IMPLEMENTED();
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}
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#else
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CUTLASS_UNUSED(smem_ptr);
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CUTLASS_NOT_IMPLEMENTED();
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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/// Partial specialization
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template <
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/// Size of the access in bytes
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int SizeInBytes>
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struct cp_async<SizeInBytes, CacheOperation::Global> {
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/// Copy
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CUTLASS_DEVICE
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cp_async(void *smem_ptr, void const *global_ptr, bool pred_guard = true) {
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#if CUDA_CP_ASYNC_ACTIVATED
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static_assert(SizeInBytes == 16,
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"cp.async only supports CacheOperation::Global when access size is 16B.");
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unsigned smem_int_ptr = cutlass_get_smem_pointer(smem_ptr);
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asm volatile(
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"{\n"
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" .reg .pred p;\n"
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" setp.ne.b32 p, %0, 0;\n"
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#if CUTLASS_ENABLE_L2_PREFETCH
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" @p cp.async.cg.shared.global.L2::128B [%1], [%2], %3;\n"
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#else
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" @p cp.async.cg.shared.global [%1], [%2], %3;\n"
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#endif
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"}\n" ::"r"((int)pred_guard),
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"r"(smem_int_ptr), "l"(global_ptr), "n"(SizeInBytes));
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#else
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using AccessType = Array<uint8_t, SizeInBytes>;
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if (pred_guard) {
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*static_cast<AccessType *>(smem_ptr) = *static_cast<AccessType const *>(global_ptr);
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}
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#endif
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}
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};
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/// Partial specialization
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template <
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/// Size of the access in bytes
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int SizeInBytes>
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struct cp_async_zfill<SizeInBytes, CacheOperation::Global> {
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/// Copy with zero fill
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CUTLASS_DEVICE
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cp_async_zfill(void *smem_ptr, void const *global_ptr, bool pred_guard = true) {
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#if CUDA_CP_ASYNC_ACTIVATED
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static_assert(SizeInBytes == 16,
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"cp.async only supports CacheOperation::Global when access size is 16B.");
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unsigned smem_int_ptr = cutlass_get_smem_pointer(smem_ptr);
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int src_in_bytes = (pred_guard ? SizeInBytes : 0);
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asm volatile(
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#if CUTLASS_ENABLE_L2_PREFETCH
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"cp.async.cg.shared.global.L2::128B [%0], [%1], %2, %3;\n" ::"r"(smem_int_ptr),
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#else
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"cp.async.cg.shared.global [%0], [%1], %2, %3;\n" ::"r"(smem_int_ptr),
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#endif
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"l"(global_ptr), "n"(SizeInBytes), "r"(src_in_bytes));
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#else
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using AccessType = Array<uint8_t, SizeInBytes>;
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if (pred_guard) {
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*static_cast<AccessType *>(smem_ptr) = *static_cast<AccessType const *>(global_ptr);
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}
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else {
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AccessType zeros;
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zeros.clear();
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*static_cast<AccessType *>(smem_ptr) = zeros;
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}
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#endif
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}
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};
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/// Partial specialization
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template <>
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struct cp_async_nan<16, CacheOperation::Global> {
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static int const kSizeInBytes = 16;
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/// Copy with nan fill
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CUTLASS_DEVICE
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cp_async_nan(void *smem_ptr, void const *global_ptr, bool pred_guard) {
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#if CUDA_CP_ASYNC_ACTIVATED
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static __constant__ uint4 OOB_NAN_F16x8 = {OOB_NAN_F16x2, OOB_NAN_F16x2,
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OOB_NAN_F16x2, OOB_NAN_F16x2};
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unsigned smem_int_ptr = cutlass_get_smem_pointer(smem_ptr);
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asm volatile(
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"{\n"
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" .reg .pred p;\n"
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" setp.ne.b32 p, %0, 0;\n"
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#if CUTLASS_ENABLE_L2_PREFETCH
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" @p cp.async.cg.shared.global.L2::128B [%1], [%2], %3;\n"
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#else
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" @p cp.async.cg.shared.global [%1], [%2], %3;\n"
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#endif
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" @!p st.shared.v4.u32 [%1], {%4, %5, %6, %7};\n"
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"}\n"
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:
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: "r"((int)pred_guard), "r"(smem_int_ptr), "l"(global_ptr),
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"n"(kSizeInBytes), "r"(OOB_NAN_F16x8.x), "r"(OOB_NAN_F16x8.y), "r"(OOB_NAN_F16x8.z),
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"r"(OOB_NAN_F16x8.w));
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#else
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CUTLASS_UNUSED(smem_ptr);
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CUTLASS_UNUSED(global_ptr);
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CUTLASS_UNUSED(pred_guard);
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CUTLASS_NOT_IMPLEMENTED();
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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/// Establishes an ordering w.r.t previously issued cp.async instructions. Does not block.
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CUTLASS_DEVICE
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void cp_async_fence() {
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#if CUDA_CP_ASYNC_ACTIVATED
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asm volatile("cp.async.commit_group;\n" ::);
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#endif
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}
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////////////////////////////////////////////////////////////////////////////////////////////////////
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/// Blocks until all but <N> previous cp.async.commit_group operations have committed.
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template <int N>
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CUTLASS_DEVICE void cp_async_wait() {
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#if CUDA_CP_ASYNC_ACTIVATED
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asm volatile("cp.async.wait_group %0;\n" ::"n"(N));
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#endif
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}
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/// Blocks until all previous cp.async.commit_group operations have committed.
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template <>
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CUTLASS_DEVICE void cp_async_wait<0>() {
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#if CUDA_CP_ASYNC_ACTIVATED
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asm volatile("cp.async.wait_all;\n" ::);
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#endif
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}
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/////////////////////////////////////////////////////////////////////////////////////////////////
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} // namespace arch
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} // namespace cutlass
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/////////////////////////////////////////////////////////////////////////////////////////////////
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