6615010cd0
CUTLASS 2.4 (Implicit GEMM Convolution) Co-authored-by: Manish Gupta <manigupta@nvidia.com>, Haicheng Wu <haichengw@nvidia.com>, Dustyn Blasig <dblasig@nvidia.com>, Andrew Kerr <akerr@nvidia.com>
149 lines
6.3 KiB
CMake
149 lines
6.3 KiB
CMake
# Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without modification, are permitted
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# provided that the following conditions are met:
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# * Redistributions of source code must retain the above copyright notice, this list of
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# conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright notice, this list of
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# conditions and the following disclaimer in the documentation and/or other materials
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# provided with the distribution.
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# * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used
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# to endorse or promote products derived from this software without specific prior written
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# permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
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# FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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# STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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add_custom_target(
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cutlass_test_unit_conv_device
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DEPENDS
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cutlass_test_unit_conv_device_simt
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cutlass_test_unit_conv_device_tensorop_f32_sm70
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cutlass_test_unit_conv_device_tensorop_f32_sm75
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cutlass_test_unit_conv_device_tensorop_f16_sm80
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cutlass_test_unit_conv_device_tensorop_f32_sm80
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cutlass_test_unit_conv_device_tensorop_f32_tf32_sm80
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cutlass_test_unit_conv_device_tensorop_s32
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cutlass_test_unit_conv_device_tensorop_s32_interleaved
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)
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add_custom_target(
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test_unit_conv_device
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DEPENDS
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test_unit_conv_device_simt
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test_unit_conv_device_tensorop_f32_sm70
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test_unit_conv_device_tensorop_f32_sm75
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test_unit_conv_device_tensorop_f16_sm80
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test_unit_conv_device_tensorop_f32_sm80
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test_unit_conv_device_tensorop_f32_tf32_sm80
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test_unit_conv_device_tensorop_s32
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test_unit_conv_device_tensorop_s32_interleaved
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)
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#
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# OpClassSimt (CUDA cores)
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#
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cutlass_test_unit_add_executable(
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cutlass_test_unit_conv_device_simt
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# F32
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conv2d_fprop_implicit_gemm_f32nhwc_f32nhwc_f32nhwc_simt_f32_sm50.cu
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conv2d_fprop_implicit_gemm_f32nhwc_f32nhwc_f32nhwc_simt_f32_sm80.cu
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conv2d_dgrad_implicit_gemm_f32nhwc_f32nhwc_f32nhwc_simt_f32_sm80.cu
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conv2d_wgrad_implicit_gemm_f32nhwc_f32nhwc_f32nhwc_simt_f32_sm80.cu
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# CF32
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conv2d_fprop_implicit_gemm_cf32nhwc_cf32nhwc_cf32nhwc_simt_f32_sm50.cu
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conv2d_dgrad_implicit_gemm_cf32nhwc_cf32nhwc_cf32nhwc_simt_f32_sm50.cu
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conv2d_wgrad_implicit_gemm_cf32nhwc_cf32nhwc_cf32nhwc_simt_f32_sm50.cu
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conv2d_fprop_implicit_gemm_cf32nhwc_cf32nhwc_cf32nhwc_simt_f32_sm80.cu
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conv2d_dgrad_implicit_gemm_cf32nhwc_cf32nhwc_cf32nhwc_simt_f32_sm80.cu
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conv2d_wgrad_implicit_gemm_cf32nhwc_cf32nhwc_cf32nhwc_simt_f32_sm80.cu
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)
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#
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# OpClassTensorOp (Tensor cores)
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#
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# Conv - F16 input, F32 output, F32 accumulation
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cutlass_test_unit_add_executable(
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cutlass_test_unit_conv_device_tensorop_f32_sm70
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conv2d_fprop_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm70.cu
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conv2d_dgrad_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm70.cu
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conv2d_wgrad_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm70.cu
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)
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# Conv2d - F16 input, F32 output, F32 accumulation - SM75
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cutlass_test_unit_add_executable(
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cutlass_test_unit_conv_device_tensorop_f32_sm75
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conv2d_fprop_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm75.cu
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conv2d_dgrad_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm75.cu
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conv2d_wgrad_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm75.cu
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)
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# Conv2d - F16 input, F16 output, F16 accumulation
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cutlass_test_unit_add_executable(
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cutlass_test_unit_conv_device_tensorop_f16_sm80
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conv2d_fprop_implicit_gemm_f16nhwc_f16nhwc_f16nhwc_tensor_op_f16_sm80.cu
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conv2d_dgrad_implicit_gemm_f16nhwc_f16nhwc_f16nhwc_tensor_op_f16_sm80.cu
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conv2d_wgrad_implicit_gemm_f16nhwc_f16nhwc_f16nhwc_tensor_op_f16_sm80.cu
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)
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# Conv2d - F16 input, F32 output, F32 accumulation
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cutlass_test_unit_add_executable(
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cutlass_test_unit_conv_device_tensorop_f32_sm80
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conv2d_fprop_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm80.cu
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conv2d_dgrad_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm80.cu
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conv2d_wgrad_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm80.cu
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conv3d_wgrad_implicit_gemm_f16ndhwc_f16ndhwc_f32ndhwc_tensor_op_f32_sm75.cu
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conv3d_wgrad_implicit_gemm_f16ndhwc_f16ndhwc_f32ndhwc_tensor_op_f32_sm80.cu
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)
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# Conv2d - TF32 input, F32 output, F32 accumulation
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cutlass_test_unit_add_executable(
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cutlass_test_unit_conv_device_tensorop_f32_tf32_sm80
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conv2d_fprop_implicit_gemm_tf32nhwc_tf32nhwc_f32nhwc_tensor_op_f32_sm80.cu
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conv2d_dgrad_implicit_gemm_tf32nhwc_tf32nhwc_f32nhwc_tensor_op_f32_sm80.cu
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conv2d_wgrad_implicit_gemm_tf32nhwc_tf32nhwc_f32nhwc_tensor_op_f32_sm80.cu
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conv3d_fprop_implicit_gemm_tf32ndhwc_tf32ndhwc_f32ndhwc_tensor_op_f32_sm80.cu
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conv3d_dgrad_implicit_gemm_tf32ndhwc_tf32ndhwc_f32ndhwc_tensor_op_f32_sm80.cu
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conv3d_wgrad_implicit_gemm_tf32ndhwc_tf32ndhwc_f32ndhwc_tensor_op_f32_sm80.cu
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)
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# Conv2d - S8 input, S32 output, S32 accumulation
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cutlass_test_unit_add_executable(
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cutlass_test_unit_conv_device_tensorop_s32
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conv2d_fprop_implicit_gemm_s8nhwc_s8nhwc_s32nhwc_tensor_op_s32_sm75.cu
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conv2d_fprop_implicit_gemm_s4nhwc_s4nhwc_s32nhwc_tensor_op_s32_sm75.cu
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conv2d_fprop_implicit_gemm_s8nhwc_s8nhwc_s32nhwc_tensor_op_s32_sm80.cu
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conv2d_fprop_implicit_gemm_s4nhwc_s4nhwc_s32nhwc_tensor_op_s32_sm80.cu
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)
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# Conv2d - S8 interleaved input, S8 interleaved output, S32 accumulation
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cutlass_test_unit_add_executable(
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cutlass_test_unit_conv_device_tensorop_s32_interleaved
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conv2d_fprop_implicit_gemm_s8ncxhwx_s8cxrskx_s8ncxhwx_tensor_op_s32_sm75.cu
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conv2d_fprop_implicit_gemm_s4ncxhwx_s4cxrskx_s4ncxhwx_tensor_op_s32_sm75.cu
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conv2d_fprop_implicit_gemm_s8ncxhwx_s8cxrskx_s8ncxhwx_tensor_op_s32_sm80.cu
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conv2d_fprop_implicit_gemm_s4ncxhwx_s4cxrskx_s4ncxhwx_tensor_op_s32_sm80.cu
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)
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