288 lines
10 KiB
CMake
288 lines
10 KiB
CMake
# Copyright (c) 2017 - 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice, this
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# list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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list(SORT CUTLASS_NVCC_ARCHS_ENABLED)
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set(CUTLASS_NVCC_ARCHS_ENABLED_REVERSED ${CUTLASS_NVCC_ARCHS_ENABLED})
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list(REVERSE CUTLASS_NVCC_ARCHS_ENABLED_REVERSED)
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list(GET CUTLASS_NVCC_ARCHS_ENABLED_REVERSED 0 CUTLASS_NVCC_MAX_ARCH)
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add_custom_target(
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cutlass_test_unit_conv_device
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DEPENDS
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cutlass_test_unit_conv_device_simt
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)
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add_custom_target(
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test_unit_conv_device
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DEPENDS
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test_unit_conv_device_simt
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)
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if (CUTLASS_NVCC_MAX_ARCH GREATER_EQUAL 70)
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add_dependencies(
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cutlass_test_unit_conv_device
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cutlass_test_unit_conv_device_tensorop_f32_sm70
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)
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add_dependencies(
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test_unit_conv_device
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test_unit_conv_device_tensorop_f32_sm70
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)
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endif()
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if (CUTLASS_NVCC_MAX_ARCH GREATER_EQUAL 75)
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add_dependencies(
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cutlass_test_unit_conv_device
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cutlass_test_unit_conv_device_tensorop_f32_sm75
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cutlass_test_unit_conv_device_tensorop_s32
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cutlass_test_unit_conv_device_tensorop_s32_interleaved
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)
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add_dependencies(
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test_unit_conv_device
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test_unit_conv_device_tensorop_f32_sm75
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test_unit_conv_device_tensorop_s32
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test_unit_conv_device_tensorop_s32_interleaved
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)
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endif()
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if (CUTLASS_NVCC_MAX_ARCH GREATER_EQUAL 80)
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add_dependencies(
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cutlass_test_unit_conv_device
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cutlass_test_unit_conv_device_tensorop_f16_sm80
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cutlass_test_unit_conv_device_tensorop_f32_sm80
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cutlass_test_unit_conv_device_tensorop_f32_tf32_sm80
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)
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add_dependencies(
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test_unit_conv_device
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test_unit_conv_device_tensorop_f16_sm80
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test_unit_conv_device_tensorop_f32_sm80
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test_unit_conv_device_tensorop_f32_tf32_sm80
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)
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endif()
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if (CUTLASS_NVCC_MAX_ARCH GREATER_EQUAL 89)
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add_dependencies(
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cutlass_test_unit_conv_device
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cutlass_test_unit_conv_device_tensorop_f8_sm89
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)
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add_dependencies(
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test_unit_conv_device
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test_unit_conv_device_tensorop_f8_sm89
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)
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endif()
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#
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# OpClassSimt (CUDA cores)
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#
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cutlass_test_unit_add_executable(
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cutlass_test_unit_conv_device_simt
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# F32
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conv2d_fprop_implicit_gemm_f32nhwc_f32nhwc_f32nhwc_simt_f32_sm50.cu
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# CF32
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conv2d_fprop_implicit_gemm_cf32nhwc_cf32nhwc_cf32nhwc_simt_f32_sm50.cu
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conv2d_dgrad_implicit_gemm_cf32nhwc_cf32nhwc_cf32nhwc_simt_f32_sm50.cu
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conv2d_wgrad_implicit_gemm_cf32nhwc_cf32nhwc_cf32nhwc_simt_f32_sm50.cu
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# F16
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conv2d_fprop_implicit_gemm_f16nhwc_f16nhwc_f16nhwc_simt_f16_sm60.cu
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depthwise_conv2d_fprop_implicit_gemm_f16nhwc_f16nhwc_f16nhwc_simt_f16_sm60.cu
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depthwise_conv2d_fprop_direct_conv_f16nhwc_f16nhwc_f16nhwc_simt_f16_sm60.cu
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depthwise_conv2d_fprop_direct_conv_fixed_stride_dilation_f16nhwc_f16nhwc_f16nhwc_simt_f16_sm60.cu
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)
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if (CUTLASS_NVCC_MAX_ARCH GREATER_EQUAL 80)
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cutlass_target_sources(
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cutlass_test_unit_conv_device_simt
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PRIVATE
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conv2d_fprop_implicit_gemm_f32nhwc_f32nhwc_f32nhwc_simt_f32_sm80.cu
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conv2d_dgrad_implicit_gemm_f32nhwc_f32nhwc_f32nhwc_simt_f32_sm80.cu
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conv2d_wgrad_implicit_gemm_f32nhwc_f32nhwc_f32nhwc_simt_f32_sm80.cu
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conv2d_fprop_implicit_gemm_cf32nhwc_cf32nhwc_cf32nhwc_simt_f32_sm80.cu
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conv2d_dgrad_implicit_gemm_cf32nhwc_cf32nhwc_cf32nhwc_simt_f32_sm80.cu
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conv2d_wgrad_implicit_gemm_cf32nhwc_cf32nhwc_cf32nhwc_simt_f32_sm80.cu
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deconv2d_implicit_gemm_f32nhwc_f32nhwc_f32nhwc_simt_f32_sm80.cu
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conv2d_fprop_with_broadcast_simt_sm80.cu
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deconv2d_with_broadcast_simt_sm80.cu
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conv3d_fprop_implicit_gemm_f32ndhwc_f32ndhwc_f32ndhwc_simt_f32_sm80.cu
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conv3d_dgrad_implicit_gemm_f32ndhwc_f32ndhwc_f32ndhwc_simt_f32_sm80.cu
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conv3d_wgrad_implicit_gemm_f32ndhwc_f32ndhwc_f32ndhwc_simt_f32_sm80.cu
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deconv3d_implicit_gemm_f32ndhwc_f32ndhwc_f32ndhwc_simt_f32_sm80.cu
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conv3d_fprop_with_broadcast_simt_sm80.cu
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deconv3d_with_broadcast_simt_sm80.cu
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)
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endif()
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#
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# OpClassTensorOp (Tensor cores)
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#
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# Conv - F16 input, F32 output, F32 accumulation
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cutlass_test_unit_add_executable(
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cutlass_test_unit_conv_device_tensorop_f32_sm70
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conv2d_fprop_with_broadcast_sm70.cu
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conv2d_fprop_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm70.cu
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conv2d_dgrad_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm70.cu
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conv2d_wgrad_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm70.cu
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)
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# Conv - F16 input, F32 output, F32 accumulation - SM75
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cutlass_test_unit_add_executable(
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cutlass_test_unit_conv_device_tensorop_f32_sm75
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conv2d_fprop_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm75.cu
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conv2d_dgrad_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm75.cu
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conv2d_wgrad_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm75.cu
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conv2d_fprop_with_broadcast_sm75.cu
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conv2d_fprop_with_reduction_sm75.cu
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conv3d_fprop_implicit_gemm_f16ndhwc_f16ndhwc_f32ndhwc_tensor_op_f32_sm75.cu
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conv3d_wgrad_implicit_gemm_f16ndhwc_f16ndhwc_f32ndhwc_tensor_op_f32_sm75.cu
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)
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if (CUTLASS_NVCC_MAX_ARCH GREATER_EQUAL 80)
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# Conv - F16 input, F16 output, F16 accumulation
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cutlass_test_unit_add_executable(
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cutlass_test_unit_conv_device_tensorop_f16_sm80
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conv2d_fprop_implicit_gemm_f16nhwc_f16nhwc_f16nhwc_tensor_op_f16_sm80.cu
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conv2d_dgrad_implicit_gemm_f16nhwc_f16nhwc_f16nhwc_tensor_op_f16_sm80.cu
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conv2d_wgrad_implicit_gemm_f16nhwc_f16nhwc_f16nhwc_tensor_op_f16_sm80.cu
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)
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# Conv - F16 input, F32 output, F32 accumulation
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cutlass_test_unit_add_executable(
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cutlass_test_unit_conv_device_tensorop_f32_sm80
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# Conv2d
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conv2d_fprop_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm80.cu
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conv2d_dgrad_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm80.cu
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conv2d_wgrad_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm80.cu
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# Conv2d (small channel count specializations)
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conv2d_fprop_fixed_channels_f16nhwc_f16nhwc_f16nhwc_tensor_op_f32_sm80.cu
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conv2d_fprop_few_channels_f16nhwc_f16nhwc_f16nhwc_tensor_op_f32_sm80.cu
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# Conv2d (Strided Dgrad)
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conv2d_strided_dgrad_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm80.cu
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conv2d_strided_dgrad_implicit_gemm_tf32nhwc_tf32nhwc_f32nhwc_tensor_op_f32_sm80.cu
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conv2d_strided_dgrad_implicit_gemm_swizzling4_sm80.cu
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# Conv3d
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conv3d_fprop_implicit_gemm_f16ndhwc_f16ndhwc_f32ndhwc_tensor_op_f32_sm80.cu
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conv3d_wgrad_implicit_gemm_f16ndhwc_f16ndhwc_f32ndhwc_tensor_op_f32_sm80.cu
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# Group Conv2d
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group_conv2d_fprop_implicit_gemm_f16nhwc_f16nhwc_f16nhwc_tensor_op_f32_sm80.cu
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)
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# Conv - TF32 input, F32 output, F32 accumulation
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cutlass_test_unit_add_executable(
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cutlass_test_unit_conv_device_tensorop_f32_tf32_sm80
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conv2d_fprop_implicit_gemm_tf32nhwc_tf32nhwc_f32nhwc_tensor_op_f32_sm80.cu
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conv2d_dgrad_implicit_gemm_tf32nhwc_tf32nhwc_f32nhwc_tensor_op_f32_sm80.cu
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conv2d_wgrad_implicit_gemm_tf32nhwc_tf32nhwc_f32nhwc_tensor_op_f32_sm80.cu
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conv3d_fprop_implicit_gemm_tf32ndhwc_tf32ndhwc_f32ndhwc_tensor_op_f32_sm80.cu
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conv3d_dgrad_implicit_gemm_tf32ndhwc_tf32ndhwc_f32ndhwc_tensor_op_f32_sm80.cu
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conv3d_wgrad_implicit_gemm_tf32ndhwc_tf32ndhwc_f32ndhwc_tensor_op_f32_sm80.cu
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)
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endif()
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if (CUTLASS_NVCC_MAX_ARCH GREATER_EQUAL 75)
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# Conv2d - S8 input, S32 output, S32 accumulation
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cutlass_test_unit_add_executable(
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cutlass_test_unit_conv_device_tensorop_s32
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conv2d_fprop_implicit_gemm_s8nhwc_s8nhwc_s32nhwc_tensor_op_s32_sm75.cu
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conv2d_fprop_implicit_gemm_s4nhwc_s4nhwc_s32nhwc_tensor_op_s32_sm75.cu
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)
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# Conv2d - S8 interleaved input, S8 interleaved output, S32 accumulation
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cutlass_test_unit_add_executable(
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cutlass_test_unit_conv_device_tensorop_s32_interleaved
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conv2d_fprop_implicit_gemm_s8ncxhwx_s8cxrskx_s8ncxhwx_tensor_op_s32_sm75.cu
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conv2d_fprop_implicit_gemm_s4ncxhwx_s4cxrskx_s4ncxhwx_tensor_op_s32_sm75.cu
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)
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if (CUTLASS_NVCC_MAX_ARCH GREATER_EQUAL 80)
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cutlass_target_sources(
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cutlass_test_unit_conv_device_tensorop_s32
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PRIVATE
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conv2d_fprop_implicit_gemm_s8nhwc_s8nhwc_s32nhwc_tensor_op_s32_sm80.cu
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conv2d_fprop_implicit_gemm_s4nhwc_s4nhwc_s32nhwc_tensor_op_s32_sm80.cu
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)
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# Conv2d - S8 interleaved input, S8 interleaved output, S32 accumulation
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cutlass_target_sources(
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cutlass_test_unit_conv_device_tensorop_s32_interleaved
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PRIVATE
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conv2d_fprop_implicit_gemm_s8ncxhwx_s8cxrskx_s8ncxhwx_tensor_op_s32_sm80.cu
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conv2d_fprop_implicit_gemm_s4ncxhwx_s4cxrskx_s4ncxhwx_tensor_op_s32_sm80.cu
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)
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endif()
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endif()
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if (CUTLASS_NVCC_MAX_ARCH GREATER_EQUAL 89)
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# Conv - F8 input, F8 output, F32 accumulation
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cutlass_test_unit_add_executable(
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cutlass_test_unit_conv_device_tensorop_f8_sm89
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conv2d_fprop_implicit_gemm_f8nhwc_f8nhwc_f8nhwc_tensor_op_f32_sm89.cu
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)
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endif()
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