8236f30675
* CUTLASS 3.4.0 * Update CHANGELOG.md --------- Co-authored-by: Pradeep Ramani <prramani@nvidia.com>
432 lines
15 KiB
C++
432 lines
15 KiB
C++
/***************************************************************************************************
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* Copyright (c) 2023 - 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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**************************************************************************************************/
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#pragma once
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#include "cutlass/fast_math.h"
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#include "cutlass/gemm_coord.hpp"
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#include "cutlass/kernel_hardware_info.hpp"
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#include "cutlass/gemm/kernel/tile_scheduler_params.h"
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#include "cute/layout.hpp"
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#include "cute/tensor.hpp"
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#include "cute/arch/cluster_sm90.hpp"
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namespace cutlass::gemm::kernel::detail {
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///////////////////////////////////////////////////////////////////////////////
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// Persistent Thread Block (TB) scheduler
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template <class GroupProblemShape>
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class PersistentTileSchedulerSm90Group {
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//
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// Data members
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//
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private:
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uint64_t current_work_linear_idx_ = 0;
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uint64_t total_grid_size_ = 0;
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// Tracking current group, its starting linear idx and total tiles
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struct GroupInfo {
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uint64_t group = 0;
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uint64_t start_linear_idx = 0;
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uint64_t total_tiles = 0;
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} current_group_info_;
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public:
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struct WorkTileInfo {
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int32_t M_idx = 0;
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int32_t N_idx = 0;
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int32_t L_idx = 0;
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bool is_valid_tile = false;
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CUTLASS_HOST_DEVICE
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bool
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is_valid() const {
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return is_valid_tile;
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}
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CUTLASS_HOST_DEVICE
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static WorkTileInfo
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invalid_work_tile() {
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return {-1, -1, -1, false};
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}
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CUTLASS_HOST_DEVICE
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bool
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is_final_split(uint32_t k_tiles_per_output_tile) const {
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return true;
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}
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CUTLASS_HOST_DEVICE
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int32_t
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reduction_subtile_idx() const {
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return -1;
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}
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};
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using ProblemShape = typename GroupProblemShape::UnderlyingProblemShape;
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using Params = PersistentTileSchedulerSm90GroupParams<ProblemShape>;
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using RasterOrder = typename Params::RasterOrder;
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using RasterOrderOptions = typename Params::RasterOrderOptions;
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struct Arguments {
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int max_swizzle_size = 1;
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// Not applying Heuristics for Grouped problems, since largest dimension can change per group
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RasterOrderOptions raster_order = RasterOrderOptions::AlongM;
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};
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// Sink scheduler params as a member
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Params scheduler_params;
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//
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// Methods
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//
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template <class TileShape, class ClusterShape>
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static Params
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to_underlying_arguments(
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GroupProblemShape problem_shapes,
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TileShape tile_shape,
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ClusterShape cluster_shape,
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[[maybe_unused]] KernelHardwareInfo const& hw_info,
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Arguments const& arguments,
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[[maybe_unused]] void* workspace=nullptr,
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[[maybe_unused]] const uint32_t epilogue_subtile = 1) {
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// We only need the tile and cluster shape during scheduler setup, so let FTAD do the magic
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static_assert(cute::is_static<TileShape>::value);
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static_assert(cute::is_static<ClusterShape>::value);
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dim3 problem_blocks = get_tiled_cta_shape_mnl(
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problem_shapes.groups(),
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reinterpret_cast<ProblemShape const*>(problem_shapes.host_problem_shapes),
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tile_shape, cluster_shape);
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Params params;
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params.initialize(
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problem_blocks,
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problem_shapes.groups(),
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reinterpret_cast<ProblemShape*>(problem_shapes.problem_shapes),
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to_gemm_coord(tile_shape),
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to_gemm_coord(cluster_shape),
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hw_info,
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arguments.max_swizzle_size,
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arguments.raster_order
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);
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return params;
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}
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CUTLASS_HOST_DEVICE
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static bool
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can_implement(Arguments const& args) {
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return true;
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}
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PersistentTileSchedulerSm90Group() = default;
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CUTLASS_DEVICE explicit PersistentTileSchedulerSm90Group(Params const& params_) : scheduler_params(params_) {
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// MSVC requires protecting use of CUDA-specific nonstandard syntax,
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// like blockIdx and gridDim, with __CUDA_ARCH__.
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#if defined(__CUDA_ARCH__)
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if (params_.raster_order_ == RasterOrder::AlongN) {
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current_work_linear_idx_ = uint64_t(blockIdx.x) + uint64_t(blockIdx.y) * uint64_t(gridDim.x);
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}
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else {
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current_work_linear_idx_ = uint64_t(blockIdx.x) * uint64_t(gridDim.y) + uint64_t(blockIdx.y);
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}
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total_grid_size_ = uint64_t(gridDim.x) * uint64_t(gridDim.y) * uint64_t(gridDim.z);
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auto cta_m = cute::size(cute::ceil_div(cute::shape<0>(params_.problem_shapes_[0]), params_.cta_shape_.m()));
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auto cta_n = cute::size(cute::ceil_div(cute::shape<1>(params_.problem_shapes_[0]), params_.cta_shape_.n()));
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current_group_info_.total_tiles = cta_m * cta_n;
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#else
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CUTLASS_ASSERT(false && "This line should never be reached");
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#endif
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}
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CUTLASS_DEVICE
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WorkTileInfo
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get_current_work() {
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return get_current_work_for_linear_idx(current_work_linear_idx_);
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}
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CUTLASS_DEVICE
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WorkTileInfo
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get_current_work_for_linear_idx(uint64_t linear_idx) {
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if (linear_idx >= scheduler_params.blocks_per_problem_) {
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return WorkTileInfo::invalid_work_tile();
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}
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uint64_t blk_per_grid_dim = scheduler_params.divmod_cluster_shape_minor_.divide(linear_idx);
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auto [work_idx_m, work_idx_n, new_group_info, valid_tile] = get_work_idx_m_and_n(blk_per_grid_dim,
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current_group_info_,
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scheduler_params.groups_,
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scheduler_params.problem_shapes_,
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scheduler_params.cta_shape_,
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scheduler_params.divmod_cluster_shape_major_,
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scheduler_params.divmod_cluster_shape_minor_,
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scheduler_params.log_swizzle_size_,
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scheduler_params.raster_order_);
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current_group_info_ = new_group_info;
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return {work_idx_m, work_idx_n, static_cast<int>(current_group_info_.group), valid_tile};
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}
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CUTLASS_DEVICE
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void
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advance_to_next_work(uint32_t advance_count = 1) {
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current_work_linear_idx_ += total_grid_size_ * uint64_t(advance_count);
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}
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// get work_idx_m, work_idx_n from blk_per_grid_dim while applying swizzle
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static CUTLASS_DEVICE
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cute::tuple<int32_t, int32_t, struct GroupInfo, bool>
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get_work_idx_m_and_n(
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uint64_t blk_per_grid_dim,
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struct GroupInfo group_info,
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int32_t total_problem_groups,
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ProblemShape* problem_shapes,
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GemmCoord cta_shape,
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FastDivmodU64Pow2 const& divmod_cluster_shape_major,
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FastDivmodU64Pow2 const& divmod_cluster_shape_minor,
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int32_t log_swizzle_size,
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RasterOrder raster_order) {
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bool valid_tile = true;
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int cta_m = cute::size(cute::ceil_div(cute::shape<0>(problem_shapes[group_info.group]), cta_shape.m()));
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int cta_n = cute::size(cute::ceil_div(cute::shape<1>(problem_shapes[group_info.group]), cta_shape.n()));
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while (group_info.start_linear_idx + group_info.total_tiles <= blk_per_grid_dim) {
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group_info.group++;
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group_info.start_linear_idx += group_info.total_tiles;
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cta_m = cute::size(cute::ceil_div(cute::shape<0>(problem_shapes[group_info.group]), cta_shape.m()));
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cta_n = cute::size(cute::ceil_div(cute::shape<1>(problem_shapes[group_info.group]), cta_shape.n()));
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group_info.total_tiles = cta_m * cta_n;
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}
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uint64_t cluster_id, cluster_major_offset = 0, cluster_minor_offset = 0;
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divmod_cluster_shape_major(cluster_id, cluster_major_offset, blk_per_grid_dim - group_info.start_linear_idx);
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auto [cta_m_in_cluster, cta_n_in_cluster, _] = cute::block_id_in_cluster();
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if (raster_order == RasterOrder::AlongN) {
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cluster_minor_offset = cta_m_in_cluster;
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}
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else {
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cluster_minor_offset = cta_n_in_cluster;
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}
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uint64_t cluster_idx_minor, cluster_idx_major;
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uint64_t cluster_idx_minor_div_swizzle, extra, offset;
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offset = cluster_id & ((1 << log_swizzle_size) - 1);
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extra = cluster_id >> log_swizzle_size;
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uint64_t curr_group_cluster_blk_major, remainder;
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divmod_cluster_shape_major(curr_group_cluster_blk_major, remainder, cta_m);
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cluster_idx_minor_div_swizzle = extra / curr_group_cluster_blk_major;
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cluster_idx_major = extra % curr_group_cluster_blk_major;
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cluster_idx_minor = cluster_idx_minor_div_swizzle * (1 << log_swizzle_size) + offset;
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auto minor_work_idx = static_cast<int32_t>(cluster_idx_minor * divmod_cluster_shape_minor.divisor +
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cluster_minor_offset);
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auto major_work_idx = static_cast<int32_t>(cluster_idx_major * divmod_cluster_shape_major.divisor +
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cluster_major_offset);
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if (raster_order == RasterOrder::AlongN) {
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return {minor_work_idx, major_work_idx, group_info, valid_tile};
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}
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else {
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return {major_work_idx, minor_work_idx, group_info, valid_tile};
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}
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}
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// Given the inputs, computes the total number of output blocks this problem will compute over
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// Note that this is only the logical size of our grid, not the physical grid we will actually launch.
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template<class BlockShape, class ClusterShape>
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CUTLASS_HOST_DEVICE static
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dim3
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get_tiled_cta_shape_mnl(int groups, ProblemShape const* problem_shapes, BlockShape cta_shape, ClusterShape cluster_shape) {
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uint32_t total_ctas = 0;
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uint32_t cta_in_N_dim = 1; // We linearize the blocks across all the problems here
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for (int group = 0; group < groups; group++) {
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auto cta_m = cute::size(cute::ceil_div(cute::shape<0>(problem_shapes[group]), cute::shape<0>(cta_shape)));
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auto cta_n = cute::size(cute::ceil_div(cute::shape<1>(problem_shapes[group]), cute::shape<1>(cta_shape)));
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total_ctas += cta_m * cta_n;
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}
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return Params::get_tiled_cta_shape_mnl(
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to_gemm_coord(cluster_shape),
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total_ctas, cta_in_N_dim
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);
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}
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// Given the inputs, computes the physical grid we should launch.
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template<class BlockShape, class ClusterShape>
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CUTLASS_HOST_DEVICE static
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dim3
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get_grid_shape(
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GroupProblemShape problem_shapes,
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BlockShape cta_shape,
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ClusterShape cluster_shape,
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KernelHardwareInfo hw_info,
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Arguments arguments,
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bool truncate_by_problem_size=true) {
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dim3 problem_blocks = get_tiled_cta_shape_mnl(
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problem_shapes.groups(),
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reinterpret_cast<ProblemShape const*>(problem_shapes.host_problem_shapes),
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cta_shape, cluster_shape);
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return Params::get_grid_shape(
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problem_blocks,
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to_gemm_coord(cluster_shape),
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hw_info,
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arguments.max_swizzle_size,
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arguments.raster_order,
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/* truncate_by_problem_size = */true
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);
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}
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// Returns whether the block assigned this work should compute the epilogue for the corresponding
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// output tile. For the basic tile scheduler, this is always true.
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CUTLASS_HOST_DEVICE
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static bool
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compute_epilogue(WorkTileInfo const&, Params const&) {
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return true;
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}
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// Performs the reduction across splits for a given output tile. Since this scheduler does
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// not split output tiles, no reduction is needed.
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template <class FrgTensorC>
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CUTLASS_DEVICE
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static void
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fixup(Params const&, WorkTileInfo const&, FrgTensorC&, uint32_t, uint32_t) {}
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// Returns whether the current WorkTileInfo passed in should continue to be used. Since
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// this scheduler only schedules work in units of single, full output tiles, the WorkTileInfo
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// passed in should not be used after having been processed.
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CUTLASS_DEVICE
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static bool
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continue_current_work(WorkTileInfo&) {
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return false;
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}
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// The basic tile scheduler does not require any additional workspace
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template <class ProblemShape, class ElementAccumulator>
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static int
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get_workspace_size(Arguments const&, ProblemShape, KernelHardwareInfo const&, uint32_t, const uint32_t = 1) {
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return 0;
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}
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template <class ProblemShape, class ElementAccumulator>
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static cutlass::Status
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initialize_workspace(Arguments const&, void*, cudaStream_t, ProblemShape, KernelHardwareInfo const&,
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uint32_t, const uint32_t = 1) {
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return Status::kSuccess;
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}
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template <class ProblemShape_MNKL, class TileShape>
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CUTLASS_HOST_DEVICE
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static int
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get_work_k_tile_count(WorkTileInfo const& work_tile_info, ProblemShape_MNKL problem_shape, TileShape tile_shape) {
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// All work units returned by this scheduler cover the entire K iteration
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// space of the output tile assigned to the work unit.
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return cute::size(cute::ceil_div(cute::get<2>(problem_shape), cute::get<2>(tile_shape)));
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}
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CUTLASS_HOST_DEVICE
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static uint32_t
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get_work_k_tile_start(WorkTileInfo const&) {
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// All work units returned by this scheduler start from K tile 0
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return 0u;
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}
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CUTLASS_DEVICE
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static bool
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need_separate_reduction(Params const& params) {
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return false;
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}
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CUTLASS_DEVICE
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bool
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is_work_tile_for_reduction(WorkTileInfo const& work_tile_info, Params const& params) {
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return false;
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}
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CUTLASS_DEVICE
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uint32_t
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epilgoue_subtile_idx(WorkTileInfo const& work_tile_info, Params const& params) const {
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return 0;
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}
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template <class FrgTensorC>
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CUTLASS_DEVICE
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void
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separate_reduction(
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Params const& params,
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WorkTileInfo const& work_tile_info,
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FrgTensorC& accumulators,
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uint32_t num_barriers,
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uint32_t barrier_idx) {
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}
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// Shares the accumulator set with peers in the global workspace
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template <class FrgTensorC>
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CUTLASS_DEVICE
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static void
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share(
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Params const& params,
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WorkTileInfo const& work_tile_info,
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FrgTensorC& accumulators,
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uint32_t num_barriers,
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uint32_t barrier_idx) {
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}
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CUTLASS_DEVICE
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static bool
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valid_warpgroup_in_work_tile(WorkTileInfo const& work_tile_info) {
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return true;
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}
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CUTLASS_DEVICE
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static bool
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requires_separate_reduction(Params const& params) {
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return false;
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}
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};
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} // namespace cutlass::gemm::kernel::detail
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