1000 lines
46 KiB
C++
1000 lines
46 KiB
C++
/******************************************************************************
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* Copyright (c) 2023, Tri Dao.
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******************************************************************************/
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#include <torch/extension.h>
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#include <ATen/cuda/CUDAContext.h>
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#include <c10/cuda/CUDAGuard.h>
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#include <cutlass/numeric_types.h>
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#include "flash.h"
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#include "static_switch.h"
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#define CHECK_SHAPE(x, ...) TORCH_CHECK(x.sizes() == torch::IntArrayRef({__VA_ARGS__}), #x " must have shape (" #__VA_ARGS__ ")")
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void set_params_fprop(Flash_fwd_params ¶ms,
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// sizes
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const size_t b,
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const size_t seqlen_q,
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const size_t seqlen_k,
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const size_t seqlen_q_rounded,
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const size_t seqlen_k_rounded,
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const size_t h,
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const size_t h_k,
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const size_t d,
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const size_t d_rounded,
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// device pointers
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const at::Tensor q,
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const at::Tensor k,
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const at::Tensor v,
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at::Tensor out,
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void *cu_seqlens_q_d,
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void *cu_seqlens_k_d,
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void *p_d,
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void *softmax_lse_d,
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float p_dropout,
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float softmax_scale,
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bool is_causal) {
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// Reset the parameters
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memset(¶ms, 0, sizeof(params));
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params.is_bf16 = q.dtype() == torch::kBFloat16;
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// Set the pointers and strides.
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params.q_ptr = q.data_ptr();
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params.k_ptr = k.data_ptr();
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params.v_ptr = v.data_ptr();
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// All stride are in elements, not bytes.
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params.q_row_stride = q.stride(-3);
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params.k_row_stride = k.stride(-3);
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params.v_row_stride = v.stride(-3);
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params.q_head_stride = q.stride(-2);
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params.k_head_stride = k.stride(-2);
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params.v_head_stride = v.stride(-2);
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params.o_ptr = out.data_ptr();
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params.o_row_stride = out.stride(-3);
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params.o_head_stride = out.stride(-2);
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if (cu_seqlens_q_d == nullptr) {
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params.q_batch_stride = q.stride(0);
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params.k_batch_stride = k.stride(0);
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params.v_batch_stride = v.stride(0);
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params.o_batch_stride = out.stride(0);
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}
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params.cu_seqlens_q = static_cast<int *>(cu_seqlens_q_d);
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params.cu_seqlens_k = static_cast<int *>(cu_seqlens_k_d);
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// P = softmax(QK^T)
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params.p_ptr = p_d;
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// Softmax sum
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params.softmax_lse_ptr = softmax_lse_d;
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// Set the dimensions.
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params.b = b;
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params.h = h;
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params.h_k = h_k;
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params.h_h_k_ratio = h / h_k;
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params.seqlen_q = seqlen_q;
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params.seqlen_k = seqlen_k;
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params.seqlen_q_rounded = seqlen_q_rounded;
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params.seqlen_k_rounded = seqlen_k_rounded;
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params.d = d;
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params.d_rounded = d_rounded;
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// Set the different scale values.
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params.scale_softmax = softmax_scale;
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params.scale_softmax_log2 = softmax_scale * M_LOG2E;
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// Set this to probability of keeping an element to simplify things.
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params.p_dropout = 1.f - p_dropout;
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// Convert p from float to int so we don't have to convert the random uint to float to compare.
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// [Minor] We want to round down since when we do the comparison we use <= instead of <
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// params.p_dropout_in_uint = uint32_t(std::floor(params.p_dropout * 4294967295.0));
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// params.p_dropout_in_uint16_t = uint16_t(std::floor(params.p_dropout * 65535.0));
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params.p_dropout_in_uint8_t = uint8_t(std::floor(params.p_dropout * 255.0));
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params.rp_dropout = 1.f / params.p_dropout;
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params.scale_softmax_rp_dropout = params.rp_dropout * params.scale_softmax;
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TORCH_CHECK(p_dropout < 1.f);
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params.is_causal = is_causal;
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}
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void set_params_dgrad(Flash_bwd_params ¶ms,
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// sizes
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const size_t b,
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const size_t seqlen_q,
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const size_t seqlen_k,
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const size_t seqlen_q_rounded,
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const size_t seqlen_k_rounded,
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const size_t h,
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const size_t h_k,
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const size_t d,
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const size_t d_rounded,
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// device pointers
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const at::Tensor q,
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const at::Tensor k,
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const at::Tensor v,
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const at::Tensor out,
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const at::Tensor dout,
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at::Tensor dq,
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at::Tensor dk,
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at::Tensor dv,
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void *cu_seqlens_q_d,
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void *cu_seqlens_k_d,
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void *dq_accum_d,
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void *dk_accum_d,
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void *dv_accum_d,
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void *softmax_lse_d,
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void *dsoftmax_sum_d,
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float p_dropout,
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float softmax_scale,
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bool is_causal) {
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set_params_fprop(params,
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b, seqlen_q, seqlen_k, seqlen_q_rounded, seqlen_k_rounded, h, h_k, d, d_rounded,
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q, k, v, out,
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cu_seqlens_q_d,
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cu_seqlens_k_d,
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nullptr,
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softmax_lse_d,
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p_dropout,
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softmax_scale,
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is_causal);
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// Set the pointers and strides.
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params.do_ptr = dout.data_ptr();
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params.do_row_stride = dout.stride(-3);
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params.do_head_stride = dout.stride(-2);
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params.dq_ptr = dq.data_ptr();
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params.dk_ptr = dk.data_ptr();
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params.dv_ptr = dv.data_ptr();
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params.dq_row_stride = dq.stride(-3);
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params.dk_row_stride = dk.stride(-3);
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params.dv_row_stride = dv.stride(-3);
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params.dq_head_stride = dq.stride(-2);
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params.dk_head_stride = dk.stride(-2);
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params.dv_head_stride = dv.stride(-2);
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if (cu_seqlens_q_d == nullptr) {
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params.do_batch_stride = dout.stride(0);
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params.dq_batch_stride = dq.stride(0);
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params.dk_batch_stride = dk.stride(0);
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params.dv_batch_stride = dv.stride(0);
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}
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params.dq_accum_ptr = dq_accum_d;
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params.dk_accum_ptr = dk_accum_d;
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params.dv_accum_ptr = dv_accum_d;
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// Softmax sum
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params.dsoftmax_sum = dsoftmax_sum_d;
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}
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void run_mha_fwd(Flash_fwd_params ¶ms, cudaStream_t stream) {
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FP16_SWITCH(!params.is_bf16, [&] {
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FWD_HEADDIM_SWITCH(params.d, [&] {
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if (params.num_splits <= 1) { // If we don't set it num_splits == 0
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run_mha_fwd_<elem_type, kHeadDim>(params, stream);
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} else {
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run_mha_fwd_splitkv_dispatch<elem_type, kHeadDim>(params, stream);
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}
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});
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});
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}
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// Find the number of splits that maximizes the occupancy. For example, if we have
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// batch * n_heads = 48 and we have 108 SMs, having 2 splits (efficiency = 0.89) is
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// better than having 3 splits (efficiency = 0.67). However, we also don't want too many
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// splits as that would incur more HBM reads/writes.
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// So we find the best efficiency, then find the smallest number of splits that gets 85%
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// of the best efficiency.
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inline int num_splits_heuristic(int batch_nheads_mblocks, int num_SMs, int num_n_blocks, int max_splits) {
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// If we have enough to almost fill the SMs, then just use 1 split
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if (batch_nheads_mblocks >= 0.8f * num_SMs) { return 1; }
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max_splits = std::min({max_splits, num_SMs, num_n_blocks});
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float max_efficiency = 0.f;
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std::vector<float> efficiency;
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efficiency.reserve(max_splits);
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auto ceildiv = [](int a, int b) { return (a + b - 1) / b; };
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// Some splits are not eligible. For example, if we have 64 blocks and choose 11 splits,
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// we'll have 6 * 10 + 4 blocks. If we choose 12 splits, we'll have 6 * 11 + (-2) blocks
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// (i.e. it's 11 splits anyway).
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// So we check if the number of blocks per split is the same as the previous num_splits.
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auto is_split_eligible = [&ceildiv, &num_n_blocks](int num_splits) {
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return num_splits == 1 || ceildiv(num_n_blocks, num_splits) != ceildiv(num_n_blocks, num_splits - 1);
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};
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for (int num_splits = 1; num_splits <= max_splits; num_splits++) {
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if (!is_split_eligible(num_splits)) {
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efficiency.push_back(0.f);
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} else {
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float n_waves = float(batch_nheads_mblocks * num_splits) / num_SMs;
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float eff = n_waves / ceil(n_waves);
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// printf("num_splits = %d, eff = %f\n", num_splits, eff);
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if (eff > max_efficiency) { max_efficiency = eff; }
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efficiency.push_back(eff);
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}
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}
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for (int num_splits = 1; num_splits <= max_splits; num_splits++) {
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if (!is_split_eligible(num_splits)) { continue; }
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if (efficiency[num_splits - 1] >= 0.85 * max_efficiency) {
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// printf("num_splits chosen = %d\n", num_splits);
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return num_splits;
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}
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}
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return 1;
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}
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std::vector<at::Tensor>
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mha_fwd(const at::Tensor &q, // batch_size x seqlen_q x num_heads x head_size
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const at::Tensor &k, // batch_size x seqlen_k x num_heads_k x head_size
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const at::Tensor &v, // batch_size x seqlen_k x num_heads_k x head_size
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c10::optional<at::Tensor> &out_, // batch_size x seqlen_q x num_heads x head_size
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const float p_dropout,
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const float softmax_scale,
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const bool is_causal,
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const bool return_softmax,
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c10::optional<at::Generator> gen_) {
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auto dprops = at::cuda::getCurrentDeviceProperties();
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// bool is_sm75 = dprops->major == 7 && dprops->minor == 5;
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bool is_sm8x = dprops->major == 8 && dprops->minor >= 0;
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bool is_sm90 = dprops->major == 9 && dprops->minor == 0;
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TORCH_CHECK(is_sm90 || is_sm8x, "FlashAttention only supports Ampere GPUs or newer.");
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// We will support Turing in the near future
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// TORCH_CHECK(is_sm90 || is_sm8x || is_sm75, "FlashAttention only supports Turing GPUs or newer.");
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auto q_dtype = q.dtype();
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TORCH_CHECK(q_dtype == torch::kFloat16 || q_dtype == torch::kBFloat16,
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"FlashAttention only support fp16 and bf16 data type");
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if (q_dtype == torch::kBFloat16) {
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TORCH_CHECK(is_sm90 || is_sm8x, "bfloat16 is only supported on Ampere GPUs or newer");
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}
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TORCH_CHECK(k.dtype() == q_dtype, "query and key must have the same dtype");
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TORCH_CHECK(v.dtype() == q_dtype, "query and value must have the same dtype");
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TORCH_CHECK(q.is_cuda(), "Input tensor must be on CUDA device");
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TORCH_CHECK(k.is_cuda(), "Input tensor must be on CUDA device");
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TORCH_CHECK(v.is_cuda(), "Input tensor must be on CUDA device");
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TORCH_CHECK(q.stride(-1) == 1, "Input tensor must have contiguous last dimension");
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TORCH_CHECK(k.stride(-1) == 1, "Input tensor must have contiguous last dimension");
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TORCH_CHECK(v.stride(-1) == 1, "Input tensor must have contiguous last dimension");
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const auto sizes = q.sizes();
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const int batch_size = sizes[0];
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const int seqlen_q = sizes[1];
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const int num_heads = sizes[2];
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const int head_size_og = sizes[3];
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const int seqlen_k = k.size(1);
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const int num_heads_k = k.size(2);
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TORCH_CHECK(batch_size > 0, "batch size must be postive");
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TORCH_CHECK(head_size_og <= 256, "FlashAttention forward only supports head dimension at most 256");
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TORCH_CHECK(num_heads % num_heads_k == 0, "Number of heads in key/value must divide number of heads in query");
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CHECK_SHAPE(q, batch_size, seqlen_q, num_heads, head_size_og);
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CHECK_SHAPE(k, batch_size, seqlen_k, num_heads_k, head_size_og);
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CHECK_SHAPE(v, batch_size, seqlen_k, num_heads_k, head_size_og);
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at::Tensor q_padded, k_padded, v_padded;
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if (head_size_og % 8 != 0) {
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q_padded = torch::nn::functional::pad(q, torch::nn::functional::PadFuncOptions({0, 8 - head_size_og % 8}));
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k_padded = torch::nn::functional::pad(k, torch::nn::functional::PadFuncOptions({0, 8 - head_size_og % 8}));
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v_padded = torch::nn::functional::pad(v, torch::nn::functional::PadFuncOptions({0, 8 - head_size_og % 8}));
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} else {
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q_padded = q;
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k_padded = k;
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v_padded = v;
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}
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at::Tensor out;
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if (out_.has_value()) {
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out = out_.value();
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TORCH_CHECK(out.dtype() == q_dtype, "Output must have the same dtype as inputs");
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TORCH_CHECK(out.is_cuda(), "Output tensor must be on CUDA device");
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TORCH_CHECK(out.stride(-1) == 1, "Output tensor must have contiguous last dimension");
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CHECK_SHAPE(out, batch_size, seqlen_q, num_heads, head_size_og);
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if (head_size_og % 8 != 0) { out = torch::empty_like(q_padded); }
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} else {
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out = torch::empty_like(q_padded);
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}
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auto round_multiple = [](int x, int m) { return (x + m - 1) / m * m; };
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const int head_size = round_multiple(head_size_og, 8);
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const int head_size_rounded = round_multiple(head_size, 32);
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const int seqlen_q_rounded = round_multiple(seqlen_q, 128);
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const int seqlen_k_rounded = round_multiple(seqlen_k, 128);
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// Otherwise the kernel will be launched from cuda:0 device
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// Cast to char to avoid compiler warning about narrowing
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at::cuda::CUDAGuard device_guard{(char)q.get_device()};
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auto opts = q.options();
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auto softmax_lse = torch::empty({batch_size, num_heads, seqlen_q}, opts.dtype(at::kFloat));
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at::Tensor p;
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// Only return softmax if there's dropout to reduce compilation time
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if (return_softmax) {
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TORCH_CHECK(p_dropout > 0.0f, "return_softmax is only supported when p_dropout > 0.0");
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p = torch::empty({ batch_size, num_heads, seqlen_q_rounded, seqlen_k_rounded }, opts);
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}
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Flash_fwd_params params;
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set_params_fprop(params,
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batch_size,
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seqlen_q, seqlen_k,
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seqlen_q_rounded, seqlen_k_rounded,
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num_heads, num_heads_k,
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head_size, head_size_rounded,
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q_padded, k_padded, v_padded, out,
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/*cu_seqlens_q_d=*/nullptr,
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/*cu_seqlens_k_d=*/nullptr,
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return_softmax ? p.data_ptr() : nullptr,
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softmax_lse.data_ptr(),
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p_dropout,
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softmax_scale,
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is_causal);
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// This needs to match with run_mha_fwd_splitkv_dispatch
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const int block_n = is_sm90 || is_sm8x
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? (head_size <= 64 ? 256 : (head_size <= 160 ? 128 : 64))
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: (head_size <= 64 ? 256 : (head_size <= 128 ? 128 : 64));
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const int num_n_blocks = (seqlen_k + block_n - 1) / block_n;
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// Technically kBlockM = 64 only for the splitKV kernels, not the standard kernel.
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// In any case we don't expect seqlen_q to be larger than 64 for inference.
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const int num_m_blocks = (seqlen_q + 64 - 1) / 64;
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params.num_splits = 1;
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if (p_dropout == 0.0f) { // SplitKV is not implemented for dropout
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params.num_splits = num_splits_heuristic(batch_size * num_heads * num_m_blocks, dprops->multiProcessorCount, num_n_blocks, 64);
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if (params.num_splits > 1) {
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at::Tensor softmax_lse_accum = torch::empty({params.num_splits, batch_size, num_heads, seqlen_q}, opts.dtype(at::kFloat));
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at::Tensor out_accum = torch::empty({params.num_splits, batch_size, num_heads, seqlen_q, head_size_rounded}, opts.dtype(at::kFloat));
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params.softmax_lseaccum_ptr = softmax_lse_accum.data_ptr();
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params.oaccum_ptr = out_accum.data_ptr();
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}
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}
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// number of times random will be generated per thread, to offset philox counter in thc random
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// state
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// We use a custom RNG that increases the offset by batch_size * nheads * 32.
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int64_t counter_offset = params.b * params.h * 32;
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auto options = torch::TensorOptions().dtype(torch::kFloat32).device(torch::kCUDA);
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auto rng_state = torch::empty({2}, options.dtype(torch::kInt64));
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// Forward kernel will populate memory with the seed and offset.
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params.rng_state = reinterpret_cast<uint64_t*>(rng_state.data_ptr());
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if (p_dropout > 0.0) {
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auto gen = at::get_generator_or_default<at::CUDAGeneratorImpl>(
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gen_, at::cuda::detail::getDefaultCUDAGenerator());
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// See Note [Acquire lock when using random generators]
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std::lock_guard<std::mutex> lock(gen->mutex_);
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params.philox_args = gen->philox_cuda_state(counter_offset);
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}
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auto stream = at::cuda::getCurrentCUDAStream().stream();
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run_mha_fwd(params, stream);
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at::Tensor out_padded = out;
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if (head_size_og % 8 != 0) {
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out = out.index({"...", torch::indexing::Slice(torch::indexing::None, head_size_og)});
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if (out_.has_value()) { out_.value().copy_(out); }
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}
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return {out, q_padded, k_padded, v_padded, out_padded, softmax_lse, p, rng_state};
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}
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std::vector<at::Tensor>
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mha_varlen_fwd(const at::Tensor &q, // total_q x num_heads x head_size, total_q := \sum_{i=0}^{b} s_i
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const at::Tensor &k, // total_k x num_heads_k x head_size, total_k := \sum_{i=0}^{b} s_i
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const at::Tensor &v, // total_k x num_heads_k x head_size, total_k := \sum_{i=0}^{b} s_i
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c10::optional<at::Tensor> &out_, // total_q x num_heads x head_size, total_k := \sum_{i=0}^{b} s_i
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const at::Tensor &cu_seqlens_q, // b+1
|
|
const at::Tensor &cu_seqlens_k, // b+1
|
|
const int max_seqlen_q,
|
|
const int max_seqlen_k,
|
|
const float p_dropout,
|
|
const float softmax_scale,
|
|
const bool zero_tensors,
|
|
const bool is_causal,
|
|
const bool return_softmax,
|
|
c10::optional<at::Generator> gen_) {
|
|
|
|
auto dprops = at::cuda::getCurrentDeviceProperties();
|
|
// bool is_sm75 = dprops->major == 7 && dprops->minor == 5;
|
|
bool is_sm8x = dprops->major == 8 && dprops->minor >= 0;
|
|
bool is_sm90 = dprops->major == 9 && dprops->minor == 0;
|
|
TORCH_CHECK(is_sm90 || is_sm8x, "FlashAttention only supports Ampere GPUs or newer.");
|
|
// We will support Turing in the near future
|
|
// TORCH_CHECK(is_sm90 || is_sm8x || is_sm75, "FlashAttention only supports Turing GPUs or newer.");
|
|
|
|
auto q_dtype = q.dtype();
|
|
TORCH_CHECK(q_dtype == torch::kFloat16 || q_dtype == torch::kBFloat16,
|
|
"FlashAttention only support fp16 and bf16 data type");
|
|
if (q_dtype == torch::kBFloat16) {
|
|
TORCH_CHECK(is_sm90 || is_sm8x, "bfloat16 is only supported on Ampere GPUs or newer");
|
|
}
|
|
TORCH_CHECK(k.dtype() == q_dtype, "query and key must have the same dtype");
|
|
TORCH_CHECK(v.dtype() == q_dtype, "query and value must have the same dtype");
|
|
TORCH_CHECK(cu_seqlens_q.dtype() == torch::kInt32, "cu_seqlens_q must have dtype int32");
|
|
TORCH_CHECK(cu_seqlens_k.dtype() == torch::kInt32, "cu_seqlens_k must have dtype int32");
|
|
|
|
TORCH_CHECK(q.is_cuda(), "Input tensor must be on CUDA device");
|
|
TORCH_CHECK(k.is_cuda(), "Input tensor must be on CUDA device");
|
|
TORCH_CHECK(v.is_cuda(), "Input tensor must be on CUDA device");
|
|
TORCH_CHECK(cu_seqlens_q.is_cuda(), "cu_seqlens_q must be on CUDA device");
|
|
TORCH_CHECK(cu_seqlens_k.is_cuda(), "cu_seqlens_k must be on CUDA device");
|
|
|
|
TORCH_CHECK(q.stride(-1) == 1, "Input tensor must have contiguous last dimension");
|
|
TORCH_CHECK(k.stride(-1) == 1, "Input tensor must have contiguous last dimension");
|
|
TORCH_CHECK(v.stride(-1) == 1, "Input tensor must have contiguous last dimension");
|
|
TORCH_CHECK(cu_seqlens_q.is_contiguous(), "cu_seqlens_q must be contiguous");
|
|
TORCH_CHECK(cu_seqlens_k.is_contiguous(), "cu_seqlens_k must be contiguous");
|
|
|
|
const auto sizes = q.sizes();
|
|
|
|
const int total_q = sizes[0];
|
|
const int batch_size = cu_seqlens_q.numel() - 1;
|
|
const int num_heads = sizes[1];
|
|
const int head_size_og = sizes[2];
|
|
const int total_k = k.size(0);
|
|
const int num_heads_k = k.size(1);
|
|
TORCH_CHECK(batch_size > 0, "batch size must be positive");
|
|
TORCH_CHECK(head_size_og <= 256, "FlashAttention forward only supports head dimension at most 256");
|
|
TORCH_CHECK(num_heads % num_heads_k == 0, "Number of heads in key/value must divide number of heads in query");
|
|
|
|
CHECK_SHAPE(q, total_q, num_heads, head_size_og);
|
|
CHECK_SHAPE(k, total_k, num_heads_k, head_size_og);
|
|
CHECK_SHAPE(v, total_k, num_heads_k, head_size_og);
|
|
CHECK_SHAPE(cu_seqlens_q, batch_size + 1);
|
|
CHECK_SHAPE(cu_seqlens_k, batch_size + 1);
|
|
|
|
at::Tensor q_padded, k_padded, v_padded;
|
|
if (head_size_og % 8 != 0) {
|
|
q_padded = torch::nn::functional::pad(q, torch::nn::functional::PadFuncOptions({0, 8 - head_size_og % 8}));
|
|
k_padded = torch::nn::functional::pad(k, torch::nn::functional::PadFuncOptions({0, 8 - head_size_og % 8}));
|
|
v_padded = torch::nn::functional::pad(v, torch::nn::functional::PadFuncOptions({0, 8 - head_size_og % 8}));
|
|
} else {
|
|
q_padded = q;
|
|
k_padded = k;
|
|
v_padded = v;
|
|
}
|
|
|
|
at::Tensor out;
|
|
if (out_.has_value()) {
|
|
out = out_.value();
|
|
TORCH_CHECK(out.dtype() == q_dtype, "Output must have the same dtype as inputs");
|
|
TORCH_CHECK(out.is_cuda(), "Output tensor must be on CUDA device");
|
|
TORCH_CHECK(out.stride(-1) == 1, "Output tensor must have contiguous last dimension");
|
|
CHECK_SHAPE(out, total_q, num_heads, head_size_og);
|
|
if (head_size_og % 8 != 0) { out = torch::empty_like(q_padded); }
|
|
} else {
|
|
out = torch::empty_like(q_padded);
|
|
}
|
|
|
|
auto round_multiple = [](int x, int m) { return (x + m - 1) / m * m; };
|
|
const int head_size = round_multiple(head_size_og, 8);
|
|
const int head_size_rounded = round_multiple(head_size, 32);
|
|
const int seqlen_q_rounded = round_multiple(max_seqlen_q, 128);
|
|
const int seqlen_k_rounded = round_multiple(max_seqlen_k, 128);
|
|
|
|
// Otherwise the kernel will be launched from cuda:0 device
|
|
// Cast to char to avoid compiler warning about narrowing
|
|
at::cuda::CUDAGuard device_guard{(char)q.get_device()};
|
|
|
|
auto opts = q.options();
|
|
|
|
auto softmax_lse = torch::empty({batch_size, num_heads, max_seqlen_q}, opts.dtype(at::kFloat));
|
|
at::Tensor p;
|
|
// Only return softmax if there's dropout to reduce compilation time
|
|
if (return_softmax) {
|
|
TORCH_CHECK(p_dropout > 0.0f, "return_softmax is only supported when p_dropout > 0.0");
|
|
p = torch::empty({ batch_size, num_heads, seqlen_q_rounded, seqlen_k_rounded }, opts);
|
|
}
|
|
|
|
if (zero_tensors) {
|
|
out.zero_();
|
|
softmax_lse.fill_(-std::numeric_limits<float>::infinity());
|
|
if (return_softmax) {p.zero_();}
|
|
}
|
|
|
|
Flash_fwd_params params;
|
|
set_params_fprop(params,
|
|
batch_size,
|
|
max_seqlen_q, max_seqlen_k,
|
|
seqlen_q_rounded, seqlen_k_rounded,
|
|
num_heads, num_heads_k,
|
|
head_size, head_size_rounded,
|
|
q_padded, k_padded, v_padded, out,
|
|
cu_seqlens_q.data_ptr(),
|
|
cu_seqlens_k.data_ptr(),
|
|
return_softmax ? p.data_ptr() : nullptr,
|
|
softmax_lse.data_ptr(),
|
|
p_dropout,
|
|
softmax_scale,
|
|
is_causal);
|
|
|
|
// number of times random will be generated per thread, to offset philox counter in thc random
|
|
// state
|
|
// We use a custom RNG that increases the offset by batch_size * nheads * 32.
|
|
int64_t counter_offset = params.b * params.h * 32;
|
|
auto options = torch::TensorOptions().dtype(torch::kFloat32).device(torch::kCUDA);
|
|
auto rng_state = torch::empty({2}, options.dtype(torch::kInt64));
|
|
// Forward kernel will populate memory with the seed and offset.
|
|
params.rng_state = reinterpret_cast<uint64_t*>(rng_state.data_ptr());
|
|
|
|
if (p_dropout > 0.0) {
|
|
auto gen = at::get_generator_or_default<at::CUDAGeneratorImpl>(
|
|
gen_, at::cuda::detail::getDefaultCUDAGenerator());
|
|
// See Note [Acquire lock when using random generators]
|
|
std::lock_guard<std::mutex> lock(gen->mutex_);
|
|
params.philox_args = gen->philox_cuda_state(counter_offset);
|
|
}
|
|
|
|
auto stream = at::cuda::getCurrentCUDAStream().stream();
|
|
run_mha_fwd(params, stream);
|
|
|
|
at::Tensor out_padded = out;
|
|
if (head_size_og % 8 != 0) {
|
|
out = out.index({"...", torch::indexing::Slice(torch::indexing::None, head_size_og)});
|
|
if (out_.has_value()) { out_.value().copy_(out); }
|
|
}
|
|
|
|
return {out, q_padded, k_padded, v_padded, out_padded, softmax_lse, p, rng_state};
|
|
}
|
|
|
|
void run_mha_bwd(Flash_bwd_params ¶ms, cudaStream_t stream, const bool configure) {
|
|
FP16_SWITCH(!params.is_bf16, [&] {
|
|
if (params.d <= 32) {
|
|
run_mha_bwd_<elem_type, 32>(params, stream, configure);
|
|
} else if (params.d <= 64) {
|
|
run_mha_bwd_<elem_type, 64>(params, stream, configure);
|
|
} else if (params.d <= 96) {
|
|
run_mha_bwd_<elem_type, 96>(params, stream, configure);
|
|
} else if (params.d <= 128) {
|
|
run_mha_bwd_<elem_type, 128>(params, stream, configure);
|
|
} else if (params.d <= 160) {
|
|
run_mha_bwd_<elem_type, 160>(params, stream, configure);
|
|
} else if (params.d <= 192) {
|
|
run_mha_bwd_<elem_type, 192>(params, stream, configure);
|
|
} else if (params.d <= 224) {
|
|
run_mha_bwd_<elem_type, 224>(params, stream, configure);
|
|
} else if (params.d <= 256) {
|
|
run_mha_bwd_<elem_type, 256>(params, stream, configure);
|
|
}
|
|
});
|
|
}
|
|
|
|
std::vector<at::Tensor>
|
|
mha_bwd(const at::Tensor &dout, // batch_size x seqlen_q x num_heads, x head_size_og
|
|
const at::Tensor &q, // batch_size x seqlen_q x num_heads x head_size
|
|
const at::Tensor &k, // batch_size x seqlen_k x num_heads_k x head_size
|
|
const at::Tensor &v, // batch_size x seqlen_k x num_heads_k x head_size
|
|
const at::Tensor &out, // batch_size x seqlen_q x num_heads x head_size
|
|
const at::Tensor &softmax_lse, // b x h x seqlen_q
|
|
c10::optional<at::Tensor> &dq_, // batch_size x seqlen_q x num_heads x head_size
|
|
c10::optional<at::Tensor> &dk_, // batch_size x seqlen_k x num_heads_k x head_size
|
|
c10::optional<at::Tensor> &dv_, // batch_size x seqlen_k x num_heads_k x head_size
|
|
const float p_dropout, // probability to drop
|
|
const float softmax_scale,
|
|
const bool is_causal,
|
|
c10::optional<at::Generator> gen_,
|
|
c10::optional<at::Tensor> &rng_state) {
|
|
auto dprops = at::cuda::getCurrentDeviceProperties();
|
|
// bool is_sm75 = dprops->major == 7 && dprops->minor == 5;
|
|
bool is_sm8x = dprops->major == 8 && dprops->minor >= 0;
|
|
bool is_sm80 = dprops->major == 8 && dprops->minor == 0;
|
|
bool is_sm90 = dprops->major == 9 && dprops->minor == 0;
|
|
TORCH_CHECK(is_sm90 || is_sm8x, "FlashAttention only supports Ampere GPUs or newer.");
|
|
// We will support Turing in the near future
|
|
// TORCH_CHECK(is_sm90 || is_sm8x || is_sm75, "FlashAttention only supports Turing GPUs or newer.");
|
|
|
|
bool is_dropout = p_dropout > 0.0;
|
|
auto stream = at::cuda::getCurrentCUDAStream().stream();
|
|
|
|
auto q_dtype = q.dtype();
|
|
TORCH_CHECK(q_dtype == torch::kFloat16 || q_dtype == torch::kBFloat16,
|
|
"FlashAttention only support fp16 and bf16 data type");
|
|
if (q_dtype == torch::kBFloat16) {
|
|
TORCH_CHECK(is_sm90 || is_sm8x, "bfloat16 is only supported on Ampere GPUs or newer");
|
|
}
|
|
TORCH_CHECK(k.dtype() == q_dtype, "query and key must have the same dtype");
|
|
TORCH_CHECK(v.dtype() == q_dtype, "query and value must have the same dtype");
|
|
TORCH_CHECK(out.dtype() == q_dtype, "query and out must have the same dtype");
|
|
TORCH_CHECK(dout.dtype() == q_dtype, "query and dout must have the same dtype");
|
|
|
|
TORCH_CHECK(q.is_cuda(), "Input tensor must be on CUDA device");
|
|
TORCH_CHECK(k.is_cuda(), "Input tensor must be on CUDA device");
|
|
TORCH_CHECK(v.is_cuda(), "Input tensor must be on CUDA device");
|
|
TORCH_CHECK(out.is_cuda(), "out tensor must be on CUDA device");
|
|
TORCH_CHECK(dout.is_cuda(), "dout tensor must be on CUDA device");
|
|
TORCH_CHECK(softmax_lse.is_cuda(), "softmax_lse tensor must be on CUDA device");
|
|
|
|
TORCH_CHECK(q.stride(-1) == 1, "Input tensor must have contiguous last dimension");
|
|
TORCH_CHECK(k.stride(-1) == 1, "Input tensor must have contiguous last dimension");
|
|
TORCH_CHECK(v.stride(-1) == 1, "Input tensor must have contiguous last dimension");
|
|
TORCH_CHECK(out.stride(-1) == 1, "out tensor must have contiguous last dimension");
|
|
TORCH_CHECK(dout.stride(-1) == 1, "dout tensor must have contiguous last dimension");
|
|
|
|
const auto sizes = q.sizes();
|
|
|
|
const int batch_size = sizes[0];
|
|
const int seqlen_q = sizes[1];
|
|
const int num_heads = sizes[2];
|
|
const int head_size_og = dout.size(3);
|
|
const int head_size = sizes[3];
|
|
const int seqlen_k = k.size(1);
|
|
const int num_heads_k = k.size(2);
|
|
TORCH_CHECK(batch_size > 0, "batch size must be positive");
|
|
TORCH_CHECK(head_size % 8 == 0, "head_size should be a multiple of 8");
|
|
TORCH_CHECK(head_size <= 256, "FlashAttention backward only supports head dimension at most 256");
|
|
if (head_size > 192) {
|
|
TORCH_CHECK(is_sm80 || is_sm90, "FlashAttention backward for head dim > 192 requires A100/A800 or H100/H800");
|
|
}
|
|
TORCH_CHECK(num_heads % num_heads_k == 0, "Number of heads in key/value must divide number of heads in query");
|
|
|
|
auto round_multiple = [](int x, int m) { return (x + m - 1) / m * m; };
|
|
const int head_size_rounded = round_multiple(head_size, 32);
|
|
const int seqlen_q_rounded = round_multiple(seqlen_q, 128);
|
|
const int seqlen_k_rounded = round_multiple(seqlen_k, 128);
|
|
|
|
TORCH_CHECK(head_size == round_multiple(head_size_og, 8), "head_size must be head_size_og rounded to a multiple of 8");
|
|
|
|
CHECK_SHAPE(q, batch_size, seqlen_q, num_heads, head_size);
|
|
CHECK_SHAPE(k, batch_size, seqlen_k, num_heads_k, head_size);
|
|
CHECK_SHAPE(v, batch_size, seqlen_k, num_heads_k, head_size);
|
|
CHECK_SHAPE(out, batch_size, seqlen_q, num_heads, head_size);
|
|
CHECK_SHAPE(dout, batch_size, seqlen_q, num_heads, head_size_og);
|
|
|
|
at::Tensor dq, dk, dv;
|
|
if (dq_.has_value()) {
|
|
dq = dq_.value();
|
|
TORCH_CHECK(dq.dtype() == q_dtype, "dq must have the same dtype as q");
|
|
TORCH_CHECK(dq.is_cuda(), "dq must be on CUDA device");
|
|
TORCH_CHECK(dq.stride(-1) == 1, "dq must have contiguous last dimension");
|
|
CHECK_SHAPE(dq, batch_size, seqlen_q, num_heads, head_size);
|
|
} else {
|
|
dq = torch::empty_like(q);
|
|
}
|
|
if (dk_.has_value()) {
|
|
dk = dk_.value();
|
|
TORCH_CHECK(dk.dtype() == q_dtype, "dk must have the same dtype as q");
|
|
TORCH_CHECK(dk.is_cuda(), "dk must be on CUDA device");
|
|
TORCH_CHECK(dk.stride(-1) == 1, "dk must have contiguous last dimension");
|
|
CHECK_SHAPE(dk, batch_size, seqlen_k, num_heads_k, head_size);
|
|
} else {
|
|
dk = torch::empty_like(k);
|
|
}
|
|
if (dv_.has_value()) {
|
|
dv = dv_.value();
|
|
TORCH_CHECK(dv.dtype() == q_dtype, "dv must have the same dtype as q");
|
|
TORCH_CHECK(dv.is_cuda(), "dv must be on CUDA device");
|
|
TORCH_CHECK(dv.stride(-1) == 1, "dv must have contiguous last dimension");
|
|
CHECK_SHAPE(dv, batch_size, seqlen_k, num_heads_k, head_size);
|
|
} else {
|
|
dv = torch::empty_like(k);
|
|
}
|
|
|
|
at::Tensor dout_padded;
|
|
if (head_size_og % 8 != 0) {
|
|
dout_padded = torch::nn::functional::pad(dout, torch::nn::functional::PadFuncOptions({0, 8 - head_size_og % 8}));
|
|
} else {
|
|
dout_padded = dout;
|
|
}
|
|
|
|
// bool loop = seqlen_k > blocksize_c;
|
|
// TODO: change later, for now set to true for simplicity
|
|
bool loop = true;
|
|
|
|
// Otherwise the kernel will be launched from cuda:0 device
|
|
// Cast to char to avoid compiler warning about narrowing
|
|
at::cuda::CUDAGuard device_guard{(char)q.get_device()};
|
|
|
|
auto opts = q.options();
|
|
auto softmax_d = torch::empty({batch_size, num_heads, seqlen_q_rounded}, opts.dtype(at::kFloat));
|
|
at::Tensor dq_accum;
|
|
at::Tensor dk_accum, dv_accum;
|
|
if (loop) {
|
|
dq_accum = torch::empty({batch_size, num_heads, seqlen_q_rounded, head_size_rounded}, opts.dtype(at::kFloat));
|
|
// dk_accum = torch::empty({batch_size, num_heads_k, seqlen_k_rounded, head_size_rounded}, opts.dtype(at::kFloat));
|
|
// dv_accum = torch::empty({batch_size, num_heads_k, seqlen_k_rounded, head_size_rounded}, opts.dtype(at::kFloat));
|
|
}
|
|
|
|
at::Tensor dk_expanded, dv_expanded;
|
|
if (num_heads_k != num_heads) { // MQA / GQA
|
|
dk_expanded = torch::empty({batch_size, seqlen_k, num_heads, head_size}, opts);
|
|
dv_expanded = torch::empty({batch_size, seqlen_k, num_heads, head_size}, opts);
|
|
} else {
|
|
dk_expanded = dk;
|
|
dv_expanded = dv;
|
|
}
|
|
|
|
Flash_bwd_params params;
|
|
|
|
set_params_dgrad(params,
|
|
batch_size,
|
|
seqlen_q, seqlen_k,
|
|
seqlen_q_rounded, seqlen_k_rounded,
|
|
num_heads, num_heads_k,
|
|
head_size, head_size_rounded,
|
|
q, k, v, out,
|
|
dout_padded, dq, dk_expanded, dv_expanded,
|
|
nullptr,
|
|
nullptr,
|
|
loop ? dq_accum.data_ptr() : nullptr,
|
|
// loop ? dk_accum.data_ptr() : nullptr,
|
|
// loop ? dv_accum.data_ptr() : nullptr,
|
|
nullptr,
|
|
nullptr,
|
|
softmax_lse.data_ptr(),
|
|
softmax_d.data_ptr(),
|
|
p_dropout,
|
|
softmax_scale,
|
|
is_causal);
|
|
|
|
auto launch = &run_mha_bwd;
|
|
// launch(params, stream, /*configure=*/true);
|
|
|
|
auto gen = at::get_generator_or_default<at::CUDAGeneratorImpl>(
|
|
gen_, at::cuda::detail::getDefaultCUDAGenerator());
|
|
|
|
// We use a custom RNG that increases the offset by batch_size * nheads * 32.
|
|
int64_t counter_offset = params.b * params.h * 32;
|
|
|
|
if ( rng_state.has_value() ) {
|
|
params.rng_state = reinterpret_cast<uint64_t*>(rng_state.value().data_ptr());
|
|
} else if( is_dropout ) {
|
|
// See Note [Acquire lock when using random generators]
|
|
std::lock_guard<std::mutex> lock(gen->mutex_);
|
|
params.philox_args = gen->philox_cuda_state(counter_offset);
|
|
auto seeds = at::cuda::philox::unpack(params.philox_args);
|
|
params.rng_state[0] = std::get<0>(seeds);
|
|
params.rng_state[1] = std::get<1>(seeds);
|
|
}
|
|
|
|
launch(params, stream, /*configure=*/false);
|
|
|
|
// For MQA/GQA we need to sum dK and dV across the groups
|
|
if (num_heads_k != num_heads) {
|
|
at::sum_out(dk, at::reshape(dk_expanded, {batch_size, seqlen_k, num_heads_k, num_heads / num_heads_k, head_size}), {3});
|
|
at::sum_out(dv, at::reshape(dv_expanded, {batch_size, seqlen_k, num_heads_k, num_heads / num_heads_k, head_size}), {3});
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|
}
|
|
if (head_size_og % 8 != 0) {
|
|
dq = dq.index({"...", torch::indexing::Slice(torch::indexing::None, head_size_og)});
|
|
dk = dk.index({"...", torch::indexing::Slice(torch::indexing::None, head_size_og)});
|
|
dv = dv.index({"...", torch::indexing::Slice(torch::indexing::None, head_size_og)});
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|
}
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|
|
|
return { dq, dk, dv, softmax_d };
|
|
}
|
|
|
|
std::vector<at::Tensor>
|
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mha_varlen_bwd(const at::Tensor &dout, // total_q x num_heads, x head_size
|
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const at::Tensor &q, // total_q x num_heads x head_size, total_q := \sum_{i=0}^{b} s_i
|
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const at::Tensor &k, // total_k x num_heads_k x head_size, total_k := \sum_{i=0}^{b} s_i
|
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const at::Tensor &v, // total_k x num_heads_k x head_size, total_k := \sum_{i=0}^{b} s_i
|
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const at::Tensor &out, // total_q x num_heads x head_size
|
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const at::Tensor &softmax_lse, // b x h x s softmax logsumexp
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|
c10::optional<at::Tensor> &dq_, // total_q x num_heads x head_size, total_q := \sum_{i=0}^{b} s_i
|
|
c10::optional<at::Tensor> &dk_, // total_k x num_heads_k x head_size, total_k := \sum_{i=0}^{b} s_i
|
|
c10::optional<at::Tensor> &dv_, // total_k x num_heads_k x head_size, total_k := \sum_{i=0}^{b} s_i
|
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const at::Tensor &cu_seqlens_q, // b+1
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const at::Tensor &cu_seqlens_k, // b+1
|
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const int max_seqlen_q,
|
|
const int max_seqlen_k, // max sequence length to choose the kernel
|
|
const float p_dropout, // probability to drop
|
|
const float softmax_scale,
|
|
const bool zero_tensors,
|
|
const bool is_causal,
|
|
c10::optional<at::Generator> gen_,
|
|
c10::optional<at::Tensor> &rng_state
|
|
) {
|
|
auto dprops = at::cuda::getCurrentDeviceProperties();
|
|
// bool is_sm75 = dprops->major == 7 && dprops->minor == 5;
|
|
bool is_sm8x = dprops->major == 8 && dprops->minor >= 0;
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|
bool is_sm80 = dprops->major == 8 && dprops->minor == 0;
|
|
bool is_sm90 = dprops->major == 9 && dprops->minor == 0;
|
|
TORCH_CHECK(is_sm90 || is_sm8x, "FlashAttention only supports Ampere GPUs or newer.");
|
|
// We will support Turing in the near future
|
|
// TORCH_CHECK(is_sm90 || is_sm8x || is_sm75, "FlashAttention only supports Turing GPUs or newer.");
|
|
bool is_dropout = p_dropout > 0.0;
|
|
auto stream = at::cuda::getCurrentCUDAStream().stream();
|
|
|
|
auto q_dtype = q.dtype();
|
|
TORCH_CHECK(q_dtype == torch::kFloat16 || q_dtype == torch::kBFloat16,
|
|
"FlashAttention only support fp16 and bf16 data type");
|
|
if (q_dtype == torch::kBFloat16) {
|
|
TORCH_CHECK(is_sm90 || is_sm8x, "bfloat16 is only supported on Ampere GPUs or newer");
|
|
}
|
|
TORCH_CHECK(k.dtype() == q_dtype, "query and key must have the same dtype");
|
|
TORCH_CHECK(v.dtype() == q_dtype, "query and value must have the same dtype");
|
|
TORCH_CHECK(out.dtype() == q_dtype, "query and out must have the same dtype");
|
|
TORCH_CHECK(dout.dtype() == q_dtype, "query and dout must have the same dtype");
|
|
TORCH_CHECK(cu_seqlens_q.dtype() == torch::kInt32, "cu_seqlens_q must have dtype int32");
|
|
TORCH_CHECK(cu_seqlens_k.dtype() == torch::kInt32, "cu_seqlens_k must have dtype int32");
|
|
|
|
TORCH_CHECK(q.is_cuda(), "Input tensor must be on CUDA device");
|
|
TORCH_CHECK(k.is_cuda(), "Input tensor must be on CUDA device");
|
|
TORCH_CHECK(v.is_cuda(), "Input tensor must be on CUDA device");
|
|
TORCH_CHECK(out.is_cuda(), "out tensor must be on CUDA device");
|
|
TORCH_CHECK(dout.is_cuda(), "dout tensor must be on CUDA device");
|
|
TORCH_CHECK(softmax_lse.is_cuda(), "softmax_lse tensor must be on CUDA device");
|
|
TORCH_CHECK(cu_seqlens_q.is_cuda(), "cu_seqlens_q must be on CUDA device");
|
|
TORCH_CHECK(cu_seqlens_k.is_cuda(), "cu_seqlens_k must be on CUDA device");
|
|
|
|
TORCH_CHECK(q.stride(-1) == 1, "Input tensor must have contiguous last dimension");
|
|
TORCH_CHECK(k.stride(-1) == 1, "Input tensor must have contiguous last dimension");
|
|
TORCH_CHECK(v.stride(-1) == 1, "Input tensor must have contiguous last dimension");
|
|
TORCH_CHECK(out.stride(-1) == 1, "out tensor must have contiguous last dimension");
|
|
TORCH_CHECK(dout.stride(-1) == 1, "dout tensor must have contiguous last dimension");
|
|
TORCH_CHECK(cu_seqlens_q.is_contiguous(), "cu_seqlens_q must be contiguous");
|
|
TORCH_CHECK(cu_seqlens_k.is_contiguous(), "cu_seqlens_k must be contiguous");
|
|
|
|
const auto sizes = q.sizes();
|
|
|
|
const int total_q = sizes[0];
|
|
const int batch_size = cu_seqlens_q.numel() - 1;
|
|
const int num_heads = sizes[1];
|
|
const int head_size_og = dout.size(2);
|
|
const int head_size = sizes[2];
|
|
const int total_k = k.size(0);
|
|
const int num_heads_k = k.size(1);
|
|
TORCH_CHECK(batch_size > 0, "batch size must be positive");
|
|
TORCH_CHECK(head_size % 8 == 0, "head_size should be a multiple of 8");
|
|
TORCH_CHECK(head_size <= 256, "FlashAttention backward only supports head dimension at most 256");
|
|
if (head_size > 192) {
|
|
TORCH_CHECK(is_sm80 || is_sm90, "FlashAttention backward for head dim > 192 requires A100/A800 or H100/H800");
|
|
}
|
|
TORCH_CHECK(num_heads % num_heads_k == 0, "Number of heads in key/value must divide number of heads in query");
|
|
|
|
auto round_multiple = [](int x, int m) { return (x + m - 1) / m * m; };
|
|
const int head_size_rounded = round_multiple(head_size, 32);
|
|
const int seqlen_q_rounded = round_multiple(max_seqlen_q, 128);
|
|
const int seqlen_k_rounded = round_multiple(max_seqlen_k, 128);
|
|
|
|
TORCH_CHECK(head_size == round_multiple(head_size_og, 8), "head_size must be head_size_og rounded to a multiple of 8");
|
|
|
|
CHECK_SHAPE(q, total_q, num_heads, head_size);
|
|
CHECK_SHAPE(k, total_k, num_heads_k, head_size);
|
|
CHECK_SHAPE(v, total_k, num_heads_k, head_size);
|
|
CHECK_SHAPE(out, total_q, num_heads, head_size);
|
|
CHECK_SHAPE(dout, total_q, num_heads, head_size_og);
|
|
CHECK_SHAPE(cu_seqlens_q, batch_size + 1);
|
|
CHECK_SHAPE(cu_seqlens_k, batch_size + 1);
|
|
|
|
at::Tensor dq, dk, dv;
|
|
if (dq_.has_value()) {
|
|
dq = dq_.value();
|
|
TORCH_CHECK(dq.dtype() == q_dtype, "dq must have the same dtype as q");
|
|
TORCH_CHECK(dq.is_cuda(), "dq must be on CUDA device");
|
|
TORCH_CHECK(dq.stride(-1) == 1, "dq must have contiguous last dimension");
|
|
CHECK_SHAPE(dq, total_q, num_heads, head_size);
|
|
} else {
|
|
dq = torch::empty_like(q);
|
|
}
|
|
if (dk_.has_value()) {
|
|
dk = dk_.value();
|
|
TORCH_CHECK(dk.dtype() == q_dtype, "dk must have the same dtype as q");
|
|
TORCH_CHECK(dk.is_cuda(), "dk must be on CUDA device");
|
|
TORCH_CHECK(dk.stride(-1) == 1, "dk must have contiguous last dimension");
|
|
CHECK_SHAPE(dk, total_k, num_heads_k, head_size);
|
|
} else {
|
|
dk = torch::empty_like(k);
|
|
}
|
|
if (dv_.has_value()) {
|
|
dv = dv_.value();
|
|
TORCH_CHECK(dv.dtype() == q_dtype, "dv must have the same dtype as q");
|
|
TORCH_CHECK(dv.is_cuda(), "dv must be on CUDA device");
|
|
TORCH_CHECK(dv.stride(-1) == 1, "dv must have contiguous last dimension");
|
|
CHECK_SHAPE(dv, total_k, num_heads_k, head_size);
|
|
} else {
|
|
dv = torch::empty_like(k);
|
|
}
|
|
|
|
at::Tensor dout_padded;
|
|
if (head_size_og % 8 != 0) {
|
|
dout_padded = torch::nn::functional::pad(dout, torch::nn::functional::PadFuncOptions({0, 8 - head_size_og % 8}));
|
|
} else {
|
|
dout_padded = dout;
|
|
}
|
|
|
|
// bool loop = max_seqlen_k > blocksize_c;
|
|
// TODO: change later, for now set to true for simplicity
|
|
bool loop = true;
|
|
|
|
// Otherwise the kernel will be launched from cuda:0 device
|
|
// Cast to char to avoid compiler warning about narrowing
|
|
at::cuda::CUDAGuard device_guard{(char)q.get_device()};
|
|
|
|
auto opts = q.options();
|
|
auto softmax_d = torch::empty({batch_size, num_heads, seqlen_q_rounded}, opts.dtype(at::kFloat));
|
|
at::Tensor dq_accum;
|
|
if (loop) {
|
|
dq_accum = torch::empty({batch_size, num_heads, seqlen_q_rounded, head_size_rounded}, opts.dtype(at::kFloat));
|
|
}
|
|
|
|
at::Tensor dk_expanded, dv_expanded;
|
|
if (num_heads_k != num_heads) { // MQA / GQA
|
|
dk_expanded = torch::empty({total_k, num_heads, head_size}, opts);
|
|
dv_expanded = torch::empty({total_k, num_heads, head_size}, opts);
|
|
} else {
|
|
dk_expanded = dk;
|
|
dv_expanded = dv;
|
|
}
|
|
|
|
if( zero_tensors ) {
|
|
dq.zero_();
|
|
dk_expanded.zero_();
|
|
dv_expanded.zero_();
|
|
softmax_d.zero_();
|
|
}
|
|
|
|
Flash_bwd_params params;
|
|
|
|
set_params_dgrad(params,
|
|
batch_size,
|
|
max_seqlen_q, max_seqlen_k,
|
|
seqlen_q_rounded, seqlen_k_rounded,
|
|
num_heads, num_heads_k,
|
|
head_size, head_size_rounded,
|
|
q, k, v, out,
|
|
dout_padded, dq, dk_expanded, dv_expanded,
|
|
cu_seqlens_q.data_ptr(),
|
|
cu_seqlens_k.data_ptr(),
|
|
loop ? dq_accum.data_ptr() : nullptr,
|
|
nullptr,
|
|
nullptr,
|
|
softmax_lse.data_ptr(),
|
|
softmax_d.data_ptr(),
|
|
p_dropout,
|
|
softmax_scale,
|
|
is_causal);
|
|
|
|
auto launch = &run_mha_bwd;
|
|
// launch(params, stream, /*configure=*/true);
|
|
|
|
auto gen = at::get_generator_or_default<at::CUDAGeneratorImpl>(
|
|
gen_, at::cuda::detail::getDefaultCUDAGenerator());
|
|
|
|
// We use a custom RNG that increases the offset by batch_size * nheads * 32.
|
|
int64_t counter_offset = params.b * params.h * 32;
|
|
|
|
if ( rng_state.has_value() ) {
|
|
params.rng_state = reinterpret_cast<uint64_t*>(rng_state.value().data_ptr());
|
|
} else if( is_dropout ) {
|
|
// See Note [Acquire lock when using random generators]
|
|
std::lock_guard<std::mutex> lock(gen->mutex_);
|
|
params.philox_args = gen->philox_cuda_state(counter_offset);
|
|
auto seeds = at::cuda::philox::unpack(params.philox_args);
|
|
params.rng_state[0] = std::get<0>(seeds);
|
|
params.rng_state[1] = std::get<1>(seeds);
|
|
}
|
|
|
|
launch(params, stream, /*configure=*/false);
|
|
|
|
// For MQA/GQA we need to sum dK and dV across the groups
|
|
if (num_heads_k != num_heads) {
|
|
at::sum_out(dk, at::reshape(dk_expanded, {total_k, num_heads_k, num_heads / num_heads_k, head_size}), {2});
|
|
at::sum_out(dv, at::reshape(dv_expanded, {total_k, num_heads_k, num_heads / num_heads_k, head_size}), {2});
|
|
}
|
|
if (head_size_og % 8 != 0) {
|
|
dq = dq.index({"...", torch::indexing::Slice(torch::indexing::None, head_size_og)});
|
|
dk = dk.index({"...", torch::indexing::Slice(torch::indexing::None, head_size_og)});
|
|
dv = dv.index({"...", torch::indexing::Slice(torch::indexing::None, head_size_og)});
|
|
}
|
|
|
|
return { dq, dk, dv, softmax_d };
|
|
}
|
|
|
|
PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
|
|
m.doc() = "FlashAttention";
|
|
m.def("fwd", &mha_fwd, "Forward pass");
|
|
m.def("varlen_fwd", &mha_varlen_fwd, "Forward pass (variable length)");
|
|
m.def("bwd", &mha_bwd, "Backward pass");
|
|
m.def("varlen_bwd", &mha_varlen_bwd, "Backward pass (variable length)");
|
|
}
|