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[Hardware][CPU][bugfix] Fix half dtype support on AVX2-only target (#10108)

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Signed-off-by: jiang1.li <jiang1.li@intel.com>
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Li, Jiang 2024-11-07 18:42:50 +08:00 committed by GitHub
parent 0dfba97b42
commit a6f332d0d9
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GPG Key ID: B5690EEEBB952194
2 changed files with 11 additions and 1 deletions
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2
cmake/cpu_extension.cmake
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@ -93,7 +93,7 @@ if (AVX512_FOUND AND NOT AVX512_DISABLED)
FetchContent_Declare( FetchContent_Declare(
oneDNN oneDNN
GIT_REPOSITORY https://github.com/oneapi-src/oneDNN.git GIT_REPOSITORY https://github.com/oneapi-src/oneDNN.git
GIT_TAG v3.5.3 GIT_TAG v3.6
GIT_PROGRESS TRUE GIT_PROGRESS TRUE
GIT_SHALLOW TRUE GIT_SHALLOW TRUE
) )

10
csrc/cpu/cpu_types_x86.hpp
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@ -432,6 +432,16 @@ struct FP32Vec16 : public Vec<FP32Vec16> {
explicit FP32Vec16(const FP32Vec8 &data) explicit FP32Vec16(const FP32Vec8 &data)
: reg_low(data.reg), reg_high(data.reg) {} : reg_low(data.reg), reg_high(data.reg) {}
explicit FP32Vec16(const FP16Vec16 &v) {
__m128i low = _mm256_extractf128_si256(v.reg, 0);
__m128i high = _mm256_extractf128_si256(v.reg, 1);
reg_low = _mm256_cvtph_ps(low);
reg_high = _mm256_cvtph_ps(high);
}
explicit FP32Vec16(const FP16Vec8 &v) : FP32Vec16(FP32Vec8(v)) {}
explicit FP32Vec16(const BF16Vec16 &v) { explicit FP32Vec16(const BF16Vec16 &v) {
__m128i low = _mm256_extractf128_si256(v.reg, 0); __m128i low = _mm256_extractf128_si256(v.reg, 0);
__m128i high = _mm256_extractf128_si256(v.reg, 1); __m128i high = _mm256_extractf128_si256(v.reg, 1);