Silencio 8435b207af [Kernel] Add punica dimension for Qwen1.5-32B LoRA (#4850) ... Co-authored-by: Silencio <silencio@adsl-99-6-187-6.dsl.irvnca.sbcglobal.net>		2024-05-16 11:16:09 -07:00
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bgmv_bf16_bf16_bf16.cu	[Kernel] Full Tensor Parallelism for LoRA Layers (#3524)	2024-04-27 00:03:48 -07:00
bgmv_bf16_fp32_bf16.cu	[Kernel] Full Tensor Parallelism for LoRA Layers (#3524)	2024-04-27 00:03:48 -07:00
bgmv_config.h	[Kernel] Add punica dimension for Qwen1.5-32B LoRA (#4850)	2024-05-16 11:16:09 -07:00
bgmv_fp16_fp16_fp16.cu	[Kernel] Full Tensor Parallelism for LoRA Layers (#3524)	2024-04-27 00:03:48 -07:00
bgmv_fp16_fp32_fp16.cu	[Kernel] Full Tensor Parallelism for LoRA Layers (#3524)	2024-04-27 00:03:48 -07:00
bgmv_fp32_bf16_bf16.cu	[Kernel] Full Tensor Parallelism for LoRA Layers (#3524)	2024-04-27 00:03:48 -07:00
bgmv_fp32_fp16_fp16.cu	[Kernel] Full Tensor Parallelism for LoRA Layers (#3524)	2024-04-27 00:03:48 -07:00
bgmv_impl.cuh	[ROCm] Add support for Punica kernels on AMD GPUs (#3140)	2024-05-09 09:19:50 -07:00
generator.py	[Kernel] Full Tensor Parallelism for LoRA Layers (#3524)	2024-04-27 00:03:48 -07:00
vec_dtypes.cuh	[ROCm] Add support for Punica kernels on AMD GPUs (#3140)	2024-05-09 09:19:50 -07:00